SC16C2552IA44,518 NXP Semiconductors, SC16C2552IA44,518 Datasheet - Page 16

• Manufacturer Part Number: SC16C2552IA44,518
• Description: IC UART DUAL SOT187-2
• Manufacturer: NXP Semiconductors

Specifications of SC16C2552IA44,518

• Features: 2 Channels
• Number Of Channels: 2, DUART
• Fifo's: 16 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935270026518; SC16C2552IA44-T; SC16C2552IA44-T

Philips Semiconductors
9397 750 11636
Product data
Table 8:
Table 9:
Bit
3
(continued)
2
1
0
FCR[7]
0
0
1
1
FIFO Control Register bits description
RCVR trigger levels
Symbol
FCR[2]
FCR[1]
FCR[0]
FCR[6]
0
1
0
1
Rev. 03 — 20 June 2003
Description
Transmit operation in mode ‘1’: When the SC16C2552 is in
FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin
will be a logic 1 when the transmit FIFO is completely full. It will be
a logic 0 if one or more FIFO locations are empty.
Receive operation in mode ‘1’: When the SC16C2552 is in FIFO
mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has
been reached, or a Receive Time-Out has occurred, the RXRDY
signal at the MF pin will go to a logic 0. Once activated, it will go to
a logic 1 after there are no more characters in the FIFO.
NOTE: The AFR register must be set to the RXRDY mode prior to
any possible reading of the RXRDY signal.
XMIT FIFO reset.
RCVR FIFO reset.
FIFOs enabled.
Logic 0 = No FIFO transmit reset (normal default condition).
Logic 1 = Clears the contents of the transmit FIFO and resets
the FIFO counter logic (the transmit shift register is not cleared
or altered). This bit will return to a logic 0 after clearing the FIFO.
Logic 0 = No FIFO receive reset (normal default condition).
Logic 1 = Clears the contents of the receive FIFO and resets the
FIFO counter logic (the receive shift register is not cleared or
altered). This bit will return to a logic 0 after clearing the FIFO.
Logic 0 = Disable the transmit and receive FIFO (normal default
condition).
Logic 1 = Enable the transmit and receive FIFO. This bit must
be a ‘1’ when other FCR bits are written to, or they will not
be programmed.
RX FIFO trigger level
01
04
08
14
Dual UART with 16-byte transmit and receive FIFOs
…continued
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
SC16C2552
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