SC16C2552IA44,518 NXP Semiconductors, SC16C2552IA44,518 Datasheet - Page 25
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SC16C2552IA44,518
Manufacturer Part Number
SC16C2552IA44,518
Description
IC UART DUAL SOT187-2
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C2552IA44529.pdf
(38 pages)
Specifications of SC16C2552IA44,518
Features
2 Channels
Number Of Channels
2, DUART
Fifo's
16 Byte
Voltage - Supply
2.5V, 3.3V, 5V
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
44-LCC (J-Lead)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935270026518
SC16C2552IA44-T
SC16C2552IA44-T
SC16C2552IA44-T
SC16C2552IA44-T
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SC16C2552IA44,518
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Philips Semiconductors
10. Dynamic characteristics
Table 25:
T
[1]
[2]
[3]
9397 750 11636
Product data
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
N
1w
3w
6s
6h
7d
7w
7h
9d
12d
12h
13d
13w
13h
15d
16s
16h
17d
18d
19d
20d
21d
22d
23d
24d
25d
26d
27d
28d
RESET
amb
, t
Applies to external clock, crystal oscillator max 24 MHz.
= 333 ns (for Baudrate
= 1 s (for Baudrate
= 4 s (for Baudrate
When in both DMA mode 0 and FIFO enable mode, the write cycle delay should be larger than one x
IOWstrobe
2w
= 40 C to +85 C; V
AC electrical characteristics
Parameter
clock pulse duration
oscillator/clock frequency
address set-up time
address hold time
IOR delay from chip select
IOR strobe width
chip select hold time from IOR
read cycle delay
delay from IOR to data
data disable time
IOW delay from chip select
IOW strobe width
chip select hold time from IOW
data set-up time
data hold time
delay from IOW to output
delay to set interrupt from Modem
input
delay to reset interrupt from IOR
delay from stop to set interrupt
delay from IOR to reset interrupt
delay from start to set interrupt
delay from IOW to transmit start
delay from IOW to reset interrupt
delay from stop to set RXRDY
delay from IOR to reset RXRDY
delay from IOW to set TXRDY
delay from start to reset TXRDY
Reset pulse width
baud rate divisor
write cycle delay
max
=
------------------------------------- -
2 Baudrate
max
max
max
= 460.8 kbits/s)
= 115.2 kbits/s)
CC
= 1.5 Mbits/s)
1
= 2.5 V, 3.3 V or 5.0 V 10%, unless otherwise specified.
max
Conditions
25 pF load
25 pF load
25 pF load
25 pF load
25 pF load
25 pF load
25 pF load
25 pF load
Rev. 03 — 20 June 2003
[1]
[3]
Dual UART with 16-byte transmit and receive FIFOs
Min
10
-
0
0
10
77
0
20
-
-
10
20
0
25
20
15
-
-
-
-
-
-
8
-
-
-
-
-
200
1
2.5 V
Max
-
48
-
-
-
-
-
-
77
15
-
-
-
-
-
-
100
100
100
1
100
100
24
100
1
100
100
8
-
2
[2]
16
1
Min
6
-
0
0
10
26
0
20
-
-
10
20
0
25
20
5
-
-
-
-
-
-
8
-
-
-
-
-
40
1
3.3 V
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Max
-
80
-
-
-
-
-
-
26
15
-
-
-
-
-
-
33
24
24
1
29
45
24
45
1
45
45
8
-
2
[2]
16
1
, clock cycle.
SC16C2552
1
Min
6
0
0
10
23
0
20
-
-
10
15
0
20
15
5
-
-
-
-
-
-
8
-
-
-
-
-
40
1
5.0 V
Max
-
80
-
-
-
-
-
-
23
15
-
-
-
-
-
-
29
23
23
1
28
40
24
40
1
40
40
8
-
2
[2]
16
1
25 of 38
Unit
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R
ns
ns
R
ns
R
ns
ns
R
ns
R
clk
clk
clk
clk
clk