SC16C2552IA44,518 NXP Semiconductors, SC16C2552IA44,518 Datasheet - Page 17

• Manufacturer Part Number: SC16C2552IA44,518
• Description: IC UART DUAL SOT187-2
• Manufacturer: NXP Semiconductors

Specifications of SC16C2552IA44,518

• Features: 2 Channels
• Number Of Channels: 2, DUART
• Fifo's: 16 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935270026518; SC16C2552IA44-T; SC16C2552IA44-T

Philips Semiconductors
9397 750 11636
Product data
7.4 Interrupt Status Register (ISR)
The SC16C2552 provides four levels of prioritized interrupts to minimize external
software interaction. The Interrupt Status Register (ISR) provides the user with four
interrupt status bits. Performing a read cycle on the ISR will provide the user with the
highest pending interrupt level to be serviced. No other interrupts are acknowledged
until the pending interrupt is serviced. Whenever the interrupt status register is read,
the interrupt status is cleared. However, it should be noted that only the current
pending interrupt is cleared by the read. A lower level interrupt may be seen after
re-reading the interrupt status bits.
(bits 0-3) for the four prioritized interrupt levels and the interrupt sources associated
with each of these interrupt levels.
Table 10:
Table 11:
Priority
level
1
2
2
3
4
Bit
7-6
5-4
3-1
0
ISR[3]
0
0
1
0
0
Interrupt source
Interrupt Status Register bits description
Symbol
ISR[7-6]
ISR[5-4]
ISR[3-1]
ISR[0]
ISR[2]
1
1
1
0
0
Rev. 03 — 20 June 2003
Description
FIFOs enabled. These bits are set to a logic 0 when the FIFOs are
not being used in the 16C450 mode. They are set to a logic 1
when the FIFOs are enabled in the SC16C2552 mode.
Not used; initialized to a logic 0.
INT priority bits 2-0. These bits indicate the source for a pending
interrupt at interrupt priority levels 1, 2, and 3 (see
INT status.
Logic 0 or cleared = default condition.
Logic 0 or cleared = default condition.
Logic 0 or cleared = default condition.
Logic 0 = An interrupt is pending and the ISR contents may be
used as a pointer to the appropriate interrupt service routine.
Logic 1 = No interrupt pending (normal default condition).
ISR[1]
1
0
0
1
0
Dual UART with 16-byte transmit and receive FIFOs
Table 10 “Interrupt source”
ISR[0]
0
0
0
0
0
Source of the interrupt
LSR (Receiver Line Status Register)
RXRDY (Received Data Ready)
RXRDY (Receive Data time-out)
TXRDY (Transmitter Holding Register Empty)
MSR (Modem Status Register)
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
SC16C2552
shows the data values
Table
10).
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