CY8C5568AXI-060 Cypress Semiconductor Corp, CY8C5568AXI-060 Datasheet - Page 22

• Manufacturer Part Number: CY8C5568AXI-060
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5568AXI-060

• Lead Free Status / Rohs Status: Compliant

Note The two V
shown in
6.2.1 Power Modes
PSoC 5 devices have four different power modes, as shown in
Table 6-2
easily provide required functionality and processing power while
simultaneously minimizing power consumption and maximizing
battery life in low power and portable devices.
PSoC 5 power modes, in order of decreasing power
consumption are:
■
■
■
■
Active is the main processing mode. Its functionality is
configurable. Each power controllable subsystem is enabled or
Document Number: 001-66235 Rev. *A
Active
Alternate active
Sleep
Hibernate
Figure
and
Table
CCD
2-4.
pins must be connected together with as short a trace as possible. A trace under the device is recommended, as
6-3. The power modes allow a design to
Vddio1
Vddio2
Vssb
0.1 µF
0.1 µF
I/O Supply
I/O Supply
Domain
Digital
PRELIMINARY
Figure 6-4. PSoC Power System
1 µF
Regulators
Digital
0.1 µF
Vddd
disabled by using separate power configuration template
registers. In alternate active mode, fewer subsystems are
enabled, reducing power. In sleep mode most resources are
disabled regardless of the template settings. Sleep mode is
optimized to provide timed sleep intervals and RTC functionality.
The lowest power mode is hibernate, which retains register and
SRAM state, but no clocks, and allows wakeup only from I/O
pins.
power modes. Sleep and hibernate modes should not be entered
until all V
Vddd
PSoC
Figure 6-5
0.1 µF
DDIO
Regulator
I/O Supply
Regulator
Hibernate
Analog
Regulator
Sleep
Domain
Analog
®
supplies are at valid voltage levels.
I/O Supply
5: CY8C55 Family Datasheet
illustrates the allowable transitions between
0.1 µF
Vddio0
Vdda
Vcca
Vssa
Vddio3
Vddio0
1 µF
0.1 µF
Vdda
0.1 µF
.
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