CY8C5568AXI-060 Cypress Semiconductor Corp, CY8C5568AXI-060 Datasheet - Page 7

• Manufacturer Part Number: CY8C5568AXI-060
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY8C5568AXI-060

• Lead Free Status / Rohs Status: Compliant

Figure 2-3
analog performance on a two-layer board.
■
■
■
For information on circuit board layout issues for mixed signals, refer to the application note
Layout Considerations for PSoC® 3 and PSoC 5.
Document Number: 001-66235 Rev. *A
Note
5. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
The two pins labeled V
The two pins labeled V
page
The two pins labeled V
(I2C0: SDA, SIO) P12[5]
(I2C0: SCL, SIO) P12[4]
21. The trace between the two V
(SWDCK, GPIO) P1[1]
(SWDIO, GPIO) P1[0]
(SWV, GPIO) P1[3]
and
Figure 2-4 on page 9
(GPIO) P2[5]
(GPIO) P2[6]
(GPIO) P2[7]
(GPIO) P6[4]
(GPIO) P6[5]
(GPIO) P6[6]
(GPIO) P6[7]
(GPIO) P5[0]
(GPIO) P5[1]
(GPIO) P5[2]
(GPIO) P5[3]
(GPIO) P1[2]
(GPIO) P1[4]
(GPIO) P1[5]
Vboost
XRES
Vssb
Vssd
Vbat
Ind
CCD
DDD
SSD
must be connected together, with capacitance added, as shown in
must be connected together.
must be connected together.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
Lines show Vddio
to I/O supply
association
show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal
CCD
pins should be as short as possible.
PRELIMINARY
Figure 2-2. 100-pin TQFP Part Pinout
TQFP
PSoC
®
5: CY8C55 Family Datasheet
AN57821 - Mixed Signal Circuit Board
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Figure 2-3
Vddio0
P0[3] (GPIO, OpAmp0-/Extref0)
P0[2] (GPIO, OpAmp0+)
P0[1] (GPIO, OpAmp0out)
P0[0] (GPIO, OpAmp2out)
P4[1] (GPIO)
P4[0] (GPIO)
P12[3] (SIO)
P12[2] (SIO)
Vssd
Vdda
Vssa
Vcca
NC
NC
NC
NC
NC
NC
P15[3] (GPIO, kHz XTAL: Xi)
P15[2] (GPIO, kHz XTAL: Xo)
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, I2C1: SCL)
P3[7] (GPIO, OpAmp3out)
P3[6] (GPIO, OpAmp1out)
and
6.2 Power System on
Page 7 of 114
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