AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 282

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AT32UC3A3128

Manufacturer Part Number
AT32UC3A3128
Description
Manufacturer
Atmel Corporation

Specifications of AT32UC3A3128

Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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282
AVR32
POPM – Pop Multiple Registers from Stack
Architecture revision:
Architecture revision1 and higher.
Description
Loads the consecutive words pointed to by SP into the registers specified in the instruction. The
PC can be loaded, resulting in a jump to the loaded value. If PC is popped, the return value in
R12 is tested and the flags are updated. R12 can optionally be updated with -1, 0 or 1. The k bit
in the instruction coding is used to optionally let the POPM instruction update the return register
R12 with the values -1, 0 or 1.
Operation:
I.
if Reglist8[PC] ∧ k == B’1
else
if Reglist8[5] == 1 then
if Reglist8[4] == 1 then
if Reglist8[3] == 1 then
if Reglist8[2] == 1 then
if Reglist8[1] == 1 then
PC ← *(SP++)
if Reglist8[LR:R12] == B’00
else if Reglist8[LR:R12] == B’01
else
Test R12 and update flags;
if Reglist8[PC] == 1 then
if Reglist8[LR] == 1 then
if Reglist8[R12] == 1 then
if Reglist8[PC] == 1 then
R11 ←*(SP++);
R10 ←*(SP++);
R9 ← *(SP++);
R8 ← *(SP++);
R7 ← *(SP++);
R6 ← *(SP++);
R5 ← *(SP++);
R4 ← *(SP++);
R3 ← *(SP++);
R12 ← 0;
R12 ← 1;
R12 ← −1;
PC ← *(SP++);
LR ← *(SP++);
R12 ←*(SP++);
Test R12 and update flags;
32000D–04/2011

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