AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 55

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AT32UC3A3128

Manufacturer Part Number
AT32UC3A3128
Description
Manufacturer
Atmel Corporation

Specifications of AT32UC3A3128

Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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6.2.2.2
6.2.2.3
6.2.2.4
6.2.2.5
6.3
32000D–04/2011
Example of MPU functionality
TLB Multiple Hit Violation
DTLB Protection Violation
ITLB Miss Violation
DTLB Miss Violation
An DTLB protection violation is issued if a data access violates access permissions. The violat-
ing access is not executed. The address of the failing instruction is placed on the system stack.
An ITLB miss violation is issued if an instruction fetch does not hit in any region. The violating
instruction is not executed. The address of the failing instruction is placed on the system stack.
An DTLB miss violation is issued if a data access does not hit in any region. The violating access
is not executed. The address of the failing instruction is placed on the system stack.
An access hit in multiple protection regions. The address of the failing instruction is placed on
the system stack. This is a critical system error that should not occur.
As an example, consider region 0. Let region 0 be of size 16 KB, thus each subregion is 1KB.
Subregion 0 has offset 0-1KB from the base address, subregion 1 has offset 1KB-2KB and so
on.
MPUAPRA and MPUAPRB each has one field per region. Each subregion in region 0 can get its
access permissions from either MPUAPRA[AP0] or MPUAPRB[AP0], this is selected by the sub-
region’s bitfield in MPUPSR0.
Let:
MPUPSR0 = {0b0000_0000_0000_0000, 0b1010_0000_1111_0101}
MPUAPRA = {A, B, C, D, E, F, G, H}
MPUAPRB = {a, b, c, d, e, f, g, h}
where {A-H, a-h} have legal values as defined in
Thus for region 0:
Table 6-4.
Subregion
0
1
2
3
4
5
6
7
Example of access rights for subregions
Access
permission
h
H
h
H
h
h
h
h
Subregion
8
9
10
11
12
13
14
15
Access
permission
H
H
H
H
H
h
H
h
Table
6-3.
AVR32
55

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