AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 71

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AT32UC3A3128

Manufacturer Part Number
AT32UC3A3128
Description
Manufacturer
Atmel Corporation

Specifications of AT32UC3A3128

Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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8.3.1.8
8.3.1.9
32000D–04/2011
INT3 Exception
INT2 Exception
The INT3 exception is generated when the INT3 input line to the core is asserted. The INT3
exception can be masked by the SR[GM] bit, and the SR[I3M] bit. Hardware automatically sets
the SR[I3M] bit when accepting an INT3 exception, inhibiting new INT3 requests when process-
ing an INT3 request.
The INT3 Exception handler address is calculated by adding EVBA to an interrupt vector offset
specified by an interrupt controller outside the core. The interrupt controller is responsible for
providing the correct offset.
Since the INT3 exception is unrelated to the instruction stream, the instructions in the pipeline
are allowed to complete. After finishing the INT3 exception routine, execution should continue at
the instruction following the last completed instruction in the instruction stream.
The INT2 exception is generated when the INT2 input line to the core is asserted. The INT2
exception can be masked by the SR[GM] bit, and the SR[I2M] bit. Hardware automatically sets
the SR[I2M] bit when accepting an INT2 exception, inhibiting new INT2 requests when process-
ing an INT2 request.
The INT2 Exception handler address is calculated by adding EVBA to an interrupt vector offset
specified by an interrupt controller outside the core. The interrupt controller is responsible for
providing the correct offset.
Since the INT2 exception is unrelated to the instruction stream, the instructions in the pipeline
are allowed to complete. After finishing the INT2 exception routine, execution should continue at
the instruction following the last completed instruction in the instruction stream.
*(--SP
*(--SP
*(--SP
*(--SP
*(--SP
*(--SP
*(--SP
*(--SP
SR[R] = 0;
SR[J] = 0;
SR[M2:M0] = B’101;
SR[I3M] = 1;
SR[I2M] = 1;
SR[I1M] = 1;
SR[I0M] = 1;
PC = EVBA + INTERRUPT_VECTOR_OFFSET;
*(--SP
*(--SP
*(--SP
*(--SP
*(--SP
*(--SP
SYS
SYS
SYS
SYS
SYS
SYS
SYS
SYS
SYS
SYS
SYS
SYS
SYS
SYS
) = R8;
) = R9;
) = R10;
) = R11;
) = R12;
) = LR;
) = PC of first noncompleted instruction;
) = SR;
) = R8;
) = R9;
) = R10;
) = R11;
) = R12;
) = LR;
AVR32
71

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