AT32UC3A3256S Atmel Corporation, AT32UC3A3256S Datasheet - Page 187
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AT32UC3A3256S
Manufacturer Part Number
AT32UC3A3256S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A3256S
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A3256S-ALUT
Manufacturer:
MOLEX
Quantity:
20 000
Part Number:
AT32UC3A3256S-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 187 of 1012
- Download datasheet (16Mb)
15.6.4.3
15.6.4.4
32072G–11/2011
NCS waveforms
Write waveforms
•NWE waveforms
Figure 15-10. READMODE = 0: Data Is Sampled by SMC Before the Rising Edge of NCS
The write protocol is similar to the read protocol. It is depicted in
write cycle starts with the address setting on the memory address bus.
The NWE signal is characterized by a setup timing, a pulse width and a hold timing.
The NWE waveforms apply to all byte-write lines in byte write access mode: NWR0 to NWR3.
The NCS signal waveforms in write operation are not the same that those applied in read opera-
tions, but are separately defined.
1. NWESETUP: the NWE setup time is defined as the setup of address and data before
2. NWEPULSE: the NWE pulse length is the time between NWE falling edge and NWE
3. NWEHOLD: the NWE hold time is defined as the hold time of address and data after
1. NCSWRSETUP: the NCS setup time is defined as the setup time of address before the
2. NCSWRPULSE: the NCS pulse length is the time between NCS falling edge and NCS
3. NCSWRHOLD: the NCS hold time is defined as the hold time of address after the NCS
A[AD_MSB:2]
NBS0, NBS1,
the NWE falling edge.
rising edge.
the NWE rising edge.
NCS falling edge.
rising edge;
rising edge.
A0, A1
CLK_SMC
D[15:0]
NRD
NCS
t
PACC
Data Sampling
Figure 15-11 on page
188. The
187
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