AT32UC3A3256S Atmel Corporation, AT32UC3A3256S Datasheet - Page 551
AT32UC3A3256S
Manufacturer Part Number
AT32UC3A3256S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A3256S
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A3256S-ALUT
Manufacturer:
MOLEX
Quantity:
20 000
Part Number:
AT32UC3A3256S-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 551 of 1012
- Download datasheet (16Mb)
Figure 25-3. Fractional Baud Rate Generator
25.6.1.4
25.6.1.5
Table 25-4.
32072G–11/2011
DI field
Di (decimal)
CLK_USART/DIV
CLK
CLK_USART
Reserved
Baud Rate in Synchronous and SPI Mode
Baud Rate in ISO 7816 Mode
Binary and Decimal Values for Di
USCLKS
0001
1
2
3
0
1
If the USART is configured to operate in synchronous mode, the selected clock is divided by the
BRGR.CD field. This does not apply when CLK is selected.
When CLK is selected the external frequency must be at least 4.5 times lower than the system
clock, and when either CLK or CLK_USART/DIV are selected, CD must be even to ensure a
50/50 duty cycle. If CLK_USART is selected, the generator ensures this regardless of value.
The ISO7816 specification defines the bit rate with the following formula:
where:
Di is a binary value encoded on a 4-bit field, named DI, as represented in
• B is the bit rate
• Di is the bit-rate adjustment factor
• Fi is the clock frequency division factor
• f is the ISO7816 clock frequency (Hz)
BaudRate
0010
16-bit Counter
CD
2
B
Modulus
=
Control
=
FP
SelectedClock
------------------------------------- -
Di
----- -
Fi
0011
×
4
f
CD
glitch-free
USCLKS = 3
logic
FP
0100
8
SYNC
0
>1
CD
0
1
0101
16
0
1
0110
OVER
32
Sampling
Divider
FIDI
1000
12
Table
0
1
SYNC
25-4.
CLK
BaudRate
Sampling
Clock
Clock
1001
20
551
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