AT32UC3A3256S Atmel Corporation, AT32UC3A3256S Datasheet - Page 540
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AT32UC3A3256S
Manufacturer Part Number
AT32UC3A3256S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A3256S
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A3256S-ALUT
Manufacturer:
MOLEX
Quantity:
20 000
Part Number:
AT32UC3A3256S-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 540 of 1012
- Download datasheet (16Mb)
24.9.13
Name:
Access Type:
Offset:
Reset value:
• RXEN: Receive Enable
• TXEN: Transmit Enable
• RXSYN: Receive Sync
• TXSYN: Transmit Sync
• CP1: Compare 1
• CP0: Compare 0
• OVRUN: Receive Overrun
• RXRDY: Receive Ready
• TXEMPTY: Transmit Empty
32072G–11/2011
31
23
15
7
-
-
-
-
This bit is set when the CR.RXEN bit is written to one.
This bit is cleared when no data are being processed and the CR.RXDIS bit has been written to one.
This bit is set when the CR.TXEN bit is written to one.
This bit is cleared when no data are being processed and the CR.TXDIS bit has been written to one.
This bit is set when a Receive Sync has occurred.
This bit is cleared when the SR register is read.
This bit is set when a Transmit Sync has occurred.
This bit is cleared when the SR register is read.
This bit is set when compare 1 has occurred.
This bit is cleared when the SR register is read.
This bit is set when compare 0 has occurred.
This bit is cleared when the SR register is read.
This bit is set when data has been loaded in the RHR register while previous data has not yet been read.
This bit is cleared when the SR register is read.
This bit is set when data has been received and loaded in the RHR register.
This bit is cleared when the RHR register is empty.
This bit is set when the last data written in the THR register has been loaded in the TSR register and last data loaded in the TSR
register has been transmitted.
This bit is cleared when data remains in the THR register or is currently transmitted from the TSR register.
Status Register
30
22
14
6
-
-
-
-
SR
Read-only
0x40
0x000000CC
OVRUN
29
21
13
5
-
-
-
RXRDY
28
20
12
4
-
-
-
RXSYN
27
19
11
3
-
-
-
TXSYN
26
18
10
2
-
-
-
TXEMPTY
RXEN
CP1
25
17
9
1
-
TXRDY
TXEN
CP0
24
16
8
0
-
540
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