AT32UC3A364S Atmel Corporation, AT32UC3A364S Datasheet - Page 218
AT32UC3A364S
Manufacturer Part Number
AT32UC3A364S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A364S
Flash (kbytes)
64 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3A364S-ALUT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 218 of 1012
- Download datasheet (16Mb)
16. SDRAM Controller (SDRAMC)
16.1
16.2
32072G–11/2011
Features
Overview
Rev: 2.2.0.4
•
•
•
•
•
•
•
•
The SDRAM Controller (SDRAMC) extends the memory capabilities of a chip by providing the
interface to an external 16-bit SDRAM device. The page size supports ranges from 2048 to 8192
and the number of columns from 256 to 2048. It supports byte (8-bit) and halfword (16-bit)
accesses.
The SDRAMC supports a read or write burst length of one location. It keeps track of the active
row in each bank, thus maximizing SDRAM performance, e.g., the application may be placed in
one bank and data in the other banks. So as to optimize performance, it is advisable to avoid
accessing different rows in the same bank.
The SDRAMC supports a CAS latency of one, two, or three and optimizes the read access
depending on the frequency.
The different modes available (self refresh, power-down, and deep power-down modes) mini-
mize power consumption on the SDRAM device.
128-Mbytes address space
Numerous configurations supported
Programming facilities
Energy-saving capabilities
Error detection
SDRAM power-up initialization by software
CAS latency of one, two, and three supported
Auto Precharge command not used
– 2K, 4K, 8K row address memory parts
– SDRAM with two or four internal banks
– SDRAM with 16-bit data path
– Word, halfword, byte access
– Automatic page break when memory boundary has been reached
– Multibank ping-pong access
– Timing parameters specified by software
– Automatic refresh operation, refresh rate is programmable
– Automatic update of DS, TCR and PASR parameters (mobile SDRAM devices)
– Self-refresh, power-down, and deep power-down modes supported
– Supports mobile SDRAM devices
– Refresh error interrupt
218
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