AT32UC3A364S Atmel Corporation, AT32UC3A364S Datasheet - Page 581
AT32UC3A364S
Manufacturer Part Number
AT32UC3A364S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A364S
Flash (kbytes)
64 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3A364S-ALUT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 581 of 1012
- Download datasheet (16Mb)
Figure 25-46. Master Node Configuration, NACT=SUBSCRIBE
Figure 25-47. Master Node Configuration, NACT=IGNORE
25.6.11.2
32072G–11/2011
TXRDY
RXRDY
LINTC
TXRDY
RXRDY
LINTC
Read
LINIR
LINIR
RHR
Write
Write
Slave Node Configuration
Break
Break
Header
This is identical to the master node configuration above, except for:
IMPORTANT: if NACT=PUBLISH, and this field is already correct, the LINMR register must still
be written with this value in order to set TXRDY, and to request the corresponding Peripheral
DMA Controller write transfer.
The different NACT settings result in the same procedure as for the master node, see
Synch
Synch
Header
• LIN mode selected in MR.MODE is slave
• When the baud rate is configured, wait until CSR.LINIR is a one, then;
• Check for LINISFE and LINPE errors, clear errors and LINIR by writing a one to RSTSTA
• Read IDCHR
• Configure the frame transfer by writing to NACT, PARDIS, CHKDIS, CHKTYPE, DLCM, and
DLC in LINMR
Protected
Protected
Identifier
Identifier
Data3
Data3
Frame slot = TFrame_Maximum
Response
Response
space
Frame slot = TFrame_Maximum
space
Frame
Frame
Data 1
Data 1
Data 1
Data N-2
Response
Data N-1
Data N-1
Response
Data N-1
Data N
Data N
Data N
Checksum
Checksum
FSDIS=1
FSDIS=1
space
frame
Inter-
space
frame
Inter-
FSDIS=0
FSDIS=0
page
579.
581
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