AT32UC3A364S Atmel Corporation, AT32UC3A364S Datasheet - Page 843
AT32UC3A364S
Manufacturer Part Number
AT32UC3A364S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A364S
Flash (kbytes)
64 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3A364S-ALUT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 843 of 1012
- Download datasheet (16Mb)
• TRTYP: Transfer Type
• TRDIR: Transfer Direction
• TRCMD: Transfer Command
• MAXLAT: Max Latency for Command to Response
• OPDCMD: Open Drain Command
• SPCMD: Special Command
32072G–11/2011
SPCMD
TRCMD
others
TRTYP
others
Writing a zero to this bit will configure the transfer direction as write transfer.
Writing a one to this bit will configure the transfer direction as read transfer.
Writing a zero to this bit will configure a 5-cycle max latency.
Writing a one to this bit will configure a 64-cycle max latency.
Writing a zero to this bit will configure the push-pull command.
Writing a one to this bit will configure the open-drain command.
0
1
2
3
4
5
0
1
2
3
0
1
2
3
4
5
Command
Not a special CMD.
Initialization CMD:
74 clock cycles for initialization sequence.
Synchronized CMD:
Wait for the end of the current data block transfer before sending the pending command.
CE-ATA Completion Signal disable Command.
The host cancels the ability for the device to return a command completion signal on the
command line.
Interrupt command:
Corresponds to the Interrupt Mode (CMD40).
Interrupt response:
Corresponds to the Interrupt Mode (CMD40).
Reserved
Transfer Type
No data transfer
Start data transfer
Stop data transfer
Reserved
Transfer Type
MMC/SDCard Single Block
MMC/SDCard Multiple Block
MMC Stream
Reserved
SDIO Byte
SDIO Block
Reserved
843
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