AT32UC3L0256 Atmel Corporation, AT32UC3L0256 Datasheet - Page 58

• Manufacturer Part Number: AT32UC3L0256
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L0256

• Flash (kbytes): 256 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

58
AVR32
The following fields exist in PCCR, see
Table 7-1.
Bit
23:18
17:12
10:8
6:4
3
2
1
0
Other
Access
Read/write
Read/write
Read/write
Read/write
Read/write
Read-0/write
Read-0/write
Read/write
Read-0/write-
0
Performance counter control register
Name
CONF1
CONF0
F
IE
S
C
R
E
-
Description
Configures which events to count with PCNT1. See Table 7-2 for a
legend.
Configures which events to count with PCNT0. See Table 7-2 for a
legend.
Interrupt flag. If read as 1, the corresponding overflow has
occurred. Bit 8 corresponds to PCCNT.
Bit 9 corresponds to PCNT0.
Bit 10 corresponds to PCNT1.
Flags are cleared by writing a 1 to the flag.
Interrupt enable. If set, an overflow of the corresponding counter
will cause an interrupt request.
Bit 4 corresponds to PCCNT.
Bit 5 corresponds to PCNT0.
Bit 6 corresponds to PCNT1.
Clock counter scaler. If set, the clock counter increments once
every 64’th clock cycle. This expands the period-to-overflow to 2
cycles.
Clock counter reset. If written to 1, the clock counter will be reset.
Performance counter reset. If written to 1, all three counters will be
reset.
Clock counter enable. If set, all three counters will count their
configured events. If cleared, the counters are disabled and will
not count.
Unused. Read as 0. Should be written as 0.
Table 7-1 on page
58.
32000D–04/2011
38