AT32UC3L064 Atmel Corporation, AT32UC3L064 Datasheet - Page 158

• Manufacturer Part Number: AT32UC3L064
• Manufacturer: Atmel Corporation

Specifications of AT32UC3L064

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Speed: No
• Usb Interface: No
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

12.6.4.3
12.6.4.4
12.6.5
12.6.6
32099G–06/2011
Divided PB Clocks
Reset Controller
Leaving Shutdown sleep mode
Special consideration regarding waking-up from Shutdown sleep mode using the WAKE_N pin
As soon as the Shutdown sleep mode is entered, all CPU and peripherals are reset to ensure a
consistent state. POR33 and RC32K are automatically disabled to save extra power
Exiting Shutdown sleep mode can be done by the events described in
Table 12-5.
When a wake-up event occurs, the regulator is turned on and the device will wait for VDDCORE
to be valid before starting. The SLEEP bit in the Reset Cause (RCAUSE) register is then set,
allowing software running on the device to distinguish between the first power-up and a wake-up
from Shutdown mode.
By default, the WAKE_N pin will only wake the device up if it is pulled low after entering Shut-
down mode. If the WAKE_N is pulled low before the Shutdown mode is entered, it will not wake
the device from the Shutdown sleep mode. In order to wake the device by pulling WAKE_N low
before entering Shutdown mode, the user has to write a one to the WAKE_N Enable bit
(AWEN.WAKENEN). In this scenario, the CPU execution will proceed with the next instruction,
and the RCAUSE register content will not be altered.
The clock generator in the Power Manager provides divided PBx clocks for use by peripherals
that require a prescaled PBx clock. This is described in the documentation for the relevant mod-
ules. The divided clocks are directly maskable, and are stopped in sleep modes where the PBx
clocks are stopped.
The Reset Controller collects the various reset sources in the system and generates hard and
soft resets for the digital logic.
Source
PA11 (WAKE_N)
RESET_N
AST
– The 32KHz RC oscillator (RC32K) must be running and stable. This is done by
internal synchronisation, this bit must be read as a one before the sleep instruction is
executed by the CPU. Refer to the System Control Interface “SCIF” chapter for more
details.
writing a one to the EN bit in the SCIF.RC32KCR register. Due to internal
synchronisation, this bit must be read as a one to ensure that the oscillator is stable
before the sleep instruction is executed by the CPU.
Events That Can Wake-Up The Device From Shutdown Mode
Pulling-down RESET_N pin will wake-up the device
The device is kept under reset until RESET_N is tied high
again
OSC32K must be set-up to use alternate pinout (XIN32_2
and XOUT32_2) Refer to the SCIF Chapter
AST must be configured to use the clock from OSC32K
AST must be configured to allow alarm, periodic, or
overflow wake-up
How
Pulling-down PA11 will wake-up the device
AT32UC3L016/32/64
Table
12-5.
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