AT32UC3L064 Atmel Corporation, AT32UC3L064 Datasheet - Page 649

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AT32UC3L064

Manufacturer Part Number
AT32UC3L064
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT32UC3L064

Flash (kbytes)
64 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
2
Uart
4
Lin
4
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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28.6.2
28.6.3
32099G–06/2011
Prescaler and Charge Length
Capacitive Count Acquisition
Because the CAT module is configured with Peripheral DMA Controller capability that can trans-
fer data from memory to MBLEN and from ACOUNT to memory, the Peripheral DMA Controller
can perform long acquisition sequences and store results in memory without CPU intervention.
Each QTouch acquisition type (autonomous QTouch, QTouch group A, and QTouch group B)
has its own prescaler. Each QTouch prescaler divides down the CLK_CAT clock to an appropri-
ate sampling frequency for its particular acquisition type. Typical frequencies are 1 MHz for
QTouch acquisition and 4MHz for QMatrix burst timing control.
Each QTouch prescaler is controlled by the DIV field in the appropriate Configuration Register 0
(ATCFG0, TGACFG0, or TGBCFG0). The QMatrix burst timing prescaler is controlled by the
DIV field in MGCFG0. Each prescaler uses the following formula to generate the sampling clock:
Sampling clock = CLK_CAT / (2(DIV+1))
The capacitive sensor charge length, discharge length, and settle length can be determined for
each acquisition type using the CHLEN, DILEN, and SELEN fields in Configuration Registers 0
and 1. The lengths are specified in terms of prescaler clocks. In addition, the QMatrix Cx dis-
charge length can be determined using the CXDILEN field in MGCFG2.
For QMatrix acquisition, the duration of CHLEN should not be set to the same value as the
period of any periodic signal on any other pin. If the duration of CHLEN is the same as the
period of a signal on another pin, it is likely that the other signal will significantly affect measure-
ments due to stray capacitive coupling. For example, if a 1 MHz signal is generated on another
pin of the chip, then CHLEN should not be 1 microsecond.
For the QMatrix method, burst and capture lengths are set for each (X,Y) pair by writing the
desired length values to the MBLEN register. The write must be done before each X line can
start its acquisition and is indicated by the status bit MBLREQ in the Status Register (SR). A
DMA handshake interface is also connected to this status bit to reduce CPU overhead during
QMatrix acquisitions.
Four burst lengths (BURST0..3) can be written at one time into the MBLEN register. If the cur-
rent configuration uses Y lines larger than Y3 the register has to be written a second time. The
first write to MBLEN specifies the burst length for Y lines 0 to 3 in the BURST0 to BURST3 fields,
respectively. The second write specifies the burst length for Y lines 4 to 7 in fields BURST0 to
BURST3, respectively, and so on.
The Y and YK pins remain clamped to ground apart from the specified number of burst pulses,
when charge is transferred and captured into the sampling capacitor.
For the QMatrix, QTouch group A, and QTouch group B types of acquisition, the module
acquires count values from the sensors, buffers them, and makes them available for reading in
the ACOUNT register. Further processing of the count values must be performed by the CPU.
When the module performs QMatrix acquisition using multiple Y lines, it starts the capture for
each Y line at the appropriate time in the burst sequence so that all captures finish simultane-
ously. For example, suppose that an acquisition is performed on Y0 and Y1 with BURST0=53
and BURST1=60. The module will first toggle the X line 7 times while capturing on Y1 while Y0
and YK0 are clamped to ground. The module will then toggle the X line 53 times while capturing
on both Y1 and Y0.
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