AT32UC3L064 Atmel Corporation, AT32UC3L064 Datasheet
AT32UC3L064
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AT32UC3L064 Summary of contents
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... Two Master and Two Slave Two-wire Interface (TWI), 400kbit/s I • One 8-channel Analog-to-digital Converter (ADC) with Bits Resolution – Internal Temperature Sensor ® ® 32-bit AVR Microcontroller 2 C-compatible ® 32-bit AVR Microcontroller AT32UC3L064 AT32UC3L032 AT32UC3L016 Preliminary 32099G–06/2011 ...
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Eight Analog Comparators (AC) with Optional Window Detection • Capacitive Touch (CAT) Module ® – Hardware Assisted Atmel AVR – Supports QTouch and QMatrix Capture from Capacitive Touch Sensors • QTouch Library Support – Capacitive Touch Buttons, Sliders, and ...
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Description The Atmel AVR32 UC RISC processor running at frequencies up to 50MHz. AVR32 high-perfor- mance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density, and ...
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The device includes six identical 16-bit Timer/Counter (TC) channels. Each channel can be inde- pendently programmed to perform frequency measurement, event counting, interval measurement, pulse generation, delay timing, and pulse width modulation. The Pulse Width Modulation controller (PWMA) provides 8-bit ...
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Overview 2.1 Block Diagram Figure 2- 32099G–06/2011 Block Diagram MCKO MDO[5..0] MSEO[1..0] EVTI_N NEXUS EVTO_N CLASS 2+ TCK JTAG OCD TDO INTERFACE TDI TMS DATAOUT aWire RESET_N M S/M SAU S CONFIGURATION HSB-PB BRIDGE B POWER MANAGER ...
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... Analog Comparators Capacitive Touch Module JTAG aWire Max Frequency Packages 32099G–06/2011 Configuration Summary AT32UC3L064 64KB 16KB Digital Frequency Locked Loop 40-150MHz (DFLL) Crystal Oscillator 3-16MHz (OSC0) Crystal Oscillator 32KHz (OSC32K) RC Oscillator 120MHz (RC120M) RC Oscillator 115kHz (RCSYS) RC Oscillator 32kHz (RC32K) ...
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Package and Pinout 3.1 Package The device pins are multiplexed with peripheral functions as described in Figure 3-1. PA15 PA16 PA17 PA19 PA18 VDDIO GND PB11 GND PA10 PA12 VDDIO 32099G–06/2011 TQFP48/QFN48 Pinout ...
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Figure 3-2. PA16 PA17 PA19 PA18 VDDIO GND PB11 GND PA10 PA12 VDDIO 32099G–06/2011 TLLGA48 Pinout AT32UC3L016/32/64 24 PA21 23 PB10 22 RESET_N 21 PB04 20 PB05 19 GND ...
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Peripheral Multiplexing on I/O lines 3.2.1 Multiplexed signals Each GPIO line can be assigned to one of the peripheral functions.The following table describes the peripheral signals multiplexed to the GPIO lines. Table 3-1. GPIO Controller Function Multiplexing G P ...
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Table 3-1. GPIO Controller Function Multiplexing Normal 40 PA19 19 VDDIO I/O Normal 25 PA20 20 VDDIN I/O Normal I/O (TWI, 24 PA21 21 VDDIN 5V tolerant SMBus) Normal 9 PA22 22 VDDIO I/O Normal 6 PB00 32 VDDIO I/O ...
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Refer to the of the TWI, 5V Tolerant, and SMBUS pins. 3.2.2 Peripheral Functions Each GPIO line can be assigned to one of several peripheral functions. The following table describes how the various peripheral functions are selected. The last listed ...
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Table 3-4. Pin MDO[2] MDO[1] MDO[0] EVTO_N MCKO MSEO[1] MSEO[0] 3.2.5 Oscillator Pinout The oscillators are not mapped to the normal GPIO functions and their muxings are controlled by registers in the System Control Interface (SCIF). Please refer to the ...
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Signal Descriptions The following table gives details on signal name classified by peripheral. Table 3-7. Signal Descriptions List Signal Name Function ACAN3 - ACAN0 Negative inputs for comparators "A" ACAP3 - ACAP0 Positive inputs for comparators "A" ACBN3 - ...
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Table 3-7. Signal Descriptions List TMS Test Mode Select RESET_N Reset PWMA35 - PWMA0 PWMA channel waveforms PWMAOD35 - PWMA channel waveforms, open drain PWMAOD0 mode GCLK4 - GCLK0 Generic Clock Output RC32OUT RC32K output at startup XIN0 Crystal 0 ...
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Table 3-7. Signal Descriptions List Universal Synchronous/Asynchronous Receiver/Transmitter - USART0, USART1, USART2, USART3 CLK Clock CTS Clear To Send RTS Request To Send RXD Receive Data TXD Transmit Data Note: 1. ADCIFB: AD3 does not exist. Table 3-8. Signal Description ...
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I/O Line Considerations 3.4.1 JTAG Pins The JTAG is enabled if TCK is low while the RESET_N pin is released. The TCK, TMS, and TDI pins have pull-up resistors when JTAG is enabled. The TCK pin always has pull-up ...
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RC32OUT Pin 3.4.8.1 Clock output at startup After power-up, the clock generated by the 32kHz RC oscillator (RC32K) will be output on PA20, even when the device is still reset by the Power-On Reset Circuitry. This clock can be ...
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Processor and Architecture Rev: 2.1.0.0 This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the AVR32 architecture. A summary of the programming model, instruction set, and MPU is pre- sented. For further details, see ...
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Load and store instructions have several different formats in order to reduce code size and speed up execution. The register file is organized as sixteen 32-bit registers and includes the Program Counter, the Link Register, and the Stack ...
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Figure 4-1. Instruction memory controller 4.3.1 Pipeline Overview AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruc- tion Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic (ALU) section, one multiply (MUL) ...
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Figure 4-2. 4.3.2 AVR32A Microarchitecture Compliance AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is tar- geted at cost-sensitive, lower-end applications like smaller microcontrollers. This microarchitecture does not provide dedicated hardware registers for shadowing of register file registers in interrupt ...
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Doubleword-sized accesses with word-aligned pointers will automatically be performed as two word-sized accesses. The following table shows the instructions with support for unaligned addresses. All other instructions require aligned addresses. Table 4-1. Instruction ld.d st.d 4.3.2.5 Unimplemented Instructions ...
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Programming Model 4.4.1 Register File Configuration The AVR32UC register file is shown below. Figure 4-3. Application Bit 31 Bit SP_APP R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC ...
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Figure 4-5. Bit 4.4.3 Processor States 4.4.3.1 Normal RISC State The AVR32 processor supports several different execution contexts as shown in Table 4-2. Priority N/A N/A Mode changes can ...
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Debug state can be entered as described in the AVR32UC Technical Reference Manual. Debug state is exited by the retd instruction. 4.4.3.3 Secure State The AVR32 can be set in a secure state, that allows a part of the code ...
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Table 4-3. Reg # 33- ...
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Table 4-3. Reg # 100 101 102 103 104 105 106 107 108 109 110 111 112-191 192-255 4.5 Exceptions and Interrupts In the AVR32 architecture, events are used as ...
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EVBA. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. The target address of the event handler is calculated as (EVBA | event_handler_offset), not (EVBA + event_handler_offset), so EVBA and exception code segments ...
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Supervisor Calls The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is designed so that privileged routines can be called from any context. This facilitates sharing of code between different execution modes. The scall mechanism ...
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An instruction B is younger than an instruction was sent down the pipeline later than A. The addresses and priority of simultaneous events are shown in the exceptions are unused in AVR32UC since ...
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Table 4-4. Priority and Handler Addresses for Events Priority Handler Address 1 0x80000000 2 Provided by OCD system 3 EVBA+0x00 4 EVBA+0x04 5 EVBA+0x08 6 EVBA+0x0C 7 EVBA+0x10 8 Autovectored 9 Autovectored 10 Autovectored 11 Autovectored 12 EVBA+0x14 13 EVBA+0x50 ...
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... Internal High-Speed SRAM, Single-cycle access at full speed – 16Kbytes (AT32UC3L064, AT32UC3L032) – 8Kbytes (AT32UC3L016) 5.2 Physical Memory Map The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they are never remapped in any way, not even in boot ...
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Peripheral Address Map Table 5-3. Peripheral Address Mapping Address 0xFFFE0000 0xFFFE0400 0xFFFE0800 0xFFFF0000 0xFFFF1000 0xFFFF1400 0xFFFF1800 0xFFFF1C00 0xFFFF2000 0xFFFF2400 0xFFFF2800 0xFFFF2C00 0xFFFF3000 0xFFFF3400 0xFFFF3800 0xFFFF3C00 0xFFFF4000 0xFFFF4400 32099G–06/2011 Peripheral Name FLASHCDW Flash Controller - FLASHCDW HMATRIX HSB Matrix - ...
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Table 5-3. Peripheral Address Mapping 0xFFFF4800 0xFFFF4C00 0xFFFF5000 0xFFFF5400 0xFFFF5800 0xFFFF5C00 0xFFFF6000 0xFFFF6400 0xFFFF6800 0xFFFF6C00 0xFFFF7000 5.4 CPU Local Bus Mapping Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to being ...
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The following GPIO registers are mapped on the local bus: Table 5-4. Port 0 1 32099G–06/2011 Local Bus Mapped GPIO Registers Register Output Driver Enable Register (ODER) Output Value Register (OVR) Pin Value Register (PVR) Output Driver Enable Register (ODER) ...
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Supply and Startup Considerations 6.1 Supply Considerations 6.1.1 Power Supplies The AT32UC3L has several types of power supply pins: •VDDIO: Powers I/O lines. Voltage is 1.8 to 3.3V nominal. •VDDIN: Powers I/O lines and the internal regulator. Voltage is ...
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Single Supply Mode In 3.3V single supply mode the internal regulator is connected to the 3.3V source (VDDIN pin) and its output feeds VDDCORE. single supply mode. All I/O lines will be powered by the same power (VDDIN=VDDIO). ...
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Single Supply Mode In 1.8V single supply mode the internal regulator is not used, and VDDIO and VDDCORE are powered by a single 1.8V supply as shown in same power (VDDIN = VDDIO = VDDCORE). Figure 6-3. 1.62-1.98V ...
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Supply Mode with 1.8V Regulated I/O Lines In this mode, the internal regulator is connected to the 3.3V source and its output is connected to both VDDCORE and VDDIO as shown in use Shutdown mode. Figure 6-4. In ...
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Power-up Sequence 6.1.4.1 Maximum Rise Rate To avoid risk of latch-up, the rise rate of the power supplies must not exceed the values described in Recommended order for power supplies is also described in this chapter. 6.1.4.2 Minimum Rise ...
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Electrical Characteristics 7.1 Disclaimer All values in this chapter are preliminary and subject to change without further notice. 7.2 Absolute Maximum Ratings* Table 7-1. Absolute Maximum Ratings Operating temperature..................................... -40°C to +85°C Storage temperature...................................... -60°C to +150°C Voltage on ...
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Table 7-3. Symbol V VDDIO V VDDIN V VDDCORE V VDDANA Note: 7.4 Maximum Clock Frequencies These parameters are given in the following conditions: • V VDDCORE • Temperature = -40°C to 85°C Table 7-4. Symbol f CPU f PBA ...
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Corresponds to the 3.3V supply mode with 1.8V regulated I/O lines, please refer to the Supply and Startup Considerations section for more details tor static current • Operating conditions external core supply – V – Corresponds to the 1.8V ...
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Table 7-5. Power Consumption for Different Operating Modes Mode Conditions -CPU running a recursive Fibonacci algorithm (1) Active -CPU running a division algorithm (1) Idle (1) Frozen (1) Standby Stop DeepStop -OSC32K and AST stopped -Internal core supply -OSC32K running ...
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Figure 7-2. 7.5.1 Peripheral Power Consumption The values in conditions. • Operating conditions internal core supply – V – V – Corresponds to the 3.3V supply mode with 1.8V regulated I/O lines, please refer to the Supply and Startup Considerations ...
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Table 7-6. Peripheral ACIFB ADCIFB AST AW USART CAT EIC FREQM GLOC GPIO PWMA SPI TC TWIM TWIS USART WDT Notes: 32099G–06/2011 Typical Current Consumption by Peripheral (1) 1. Includes the current consumption on VDDANA and ADVREFP. 2. These ...
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I/O Pin Characteristics Table 7-7. Normal I/O Pin Characteristics Symbol Parameter R Pull-up resistance PULLUP V Input low-level voltage IL V Input high-level voltage IH V Output low-level voltage OL V Output high-level voltage OH (2) f Output frequency ...
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Table 7-8. High-drive I/O Pin Characteristics Symbol Parameter V Input high-level voltage IH V Output low-level voltage OL V Output high-level voltage OH Output frequency, all High- f drive I/O pins, except MAX (2) PA08 and PA09 Rise time, all ...
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Table 7-9. High-drive I/O, 5V Tolerant, Pin Characteristics Symbol Parameter V Output high-level voltage OH (2) f Output frequency MAX (2) t Rise time RISE (2) t Fall time FALL I Input leakage current LEAK C Input capacitance IN Notes: ...
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Oscillator Characteristics 7.7.1 Oscillator 0 (OSC0) Characteristics 7.7.1.1 Digital Clock Characteristics The following table describes the characteristics for the oscillator when a digital clock is applied on XIN. Table 7-11. Digital Clock Characteristics Symbol Parameter f XIN clock frequency ...
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Figure 7-3. UC3L 7.7.2 32KHz Crystal Oscillator (OSC32K) Characteristics Figure 7-3 must choose a crystal oscillator where the crystal load capacitance C in the table. The exact value of C Table 7-13. 32 KHz Crystal Oscillator Characteristics Symbol Parameter f ...
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Digital Frequency Locked Loop (DFLL) Characteristics Table 7-14. Digital Frequency Locked Loop Characteristics Symbol Parameter (2) f Output frequency OUT f Reference frequency REF FINE resolution Frequency drift over voltage and temperature (2) Accuracy I Power consumption DFLL (2) ...
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Figure 7-4. DFLL Open Loop Frequency Variation 160 150 140 130 120 110 100 90 80 -40 -20 Note: 1. The plot shows a typical behaviour for coarse = 99 and fine = 255 in open loop mode. 7.7.4 120MHz ...
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RC Oscillator (RC32K) Characteristics Table 7-16. 32kHz RC Oscillator Characteristics Symbol Parameter (1) f Output frequency OUT I Current consumption RC32K t Startup time STARTUP Note: 1. These values are based on simulation and characterization of other AVR ...
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Table 7-20. Flash Endurance and Data Retention Symbol Parameter N Array endurance (write/page) FARRAY N General Purpose fuses endurance (write/bit) FFUSE t Data retention RET 7.9 Analog Characteristics 7.9.1 Voltage Regulator Characteristics Table 7-21. VREG Electrical Characteristics Symbol Parameter V ...
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Power-on Reset 18 Characteristics Table 7-23. POR18 Characteristics Symbol Parameter V Voltage threshold on V POT+ V Voltage threshold on V POT- t Detection time DET Figure 7-5. V POT+ V POT- 32099G–06/2011 Condition rising VDDCORE falling VDDCORE Time ...
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Power-on Reset 33 Characteristics Table 7-24. POR33 Characteristics Symbol Parameter V Voltage threshold on V POT+ V Voltage threshold on V POT- t Detection time DET I Current consumption POR33 t Startup time STARTUP Figure 7-6. V POT+ V ...
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Table 7-26. BOD Characteristics Symbol Parameter V BOD hysteresis HYST t Detection time DET I Current consumption BOD t Startup time STARTUP 7.9.5 Supply Monitor 33 Characteristics Table 7-27. SM33 Characteristics Symbol Parameter V Voltage threshold TH Step size, between ...
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Analog to Digital Converter Characteristics Table 7-28. ADC Characteristics Symbol Parameter f ADC clock frequency ADC t Startup time STARTUP t Conversion time (latency) CONV Throughput rate V Reference voltage range ADVREFP I Current consumption on V ADC Current ...
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Figure 7- The minimum sample and hold time (in ns) can be found using this formula: t SAMPLEHOLD Where n is the number of bits in the conversion. ADCIFB ACR register. Please refer to the ADCIFB chapter for ...
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Temperature Sensor Characteristics Table 7-32. Temperature Sensor Characteristics Symbol Parameter Gradient I Current consumption TS t Startup time STARTUP Note: 1. The Temperature Sensor is not calibrated. The accuracy of the Temperature Sensor is governed by the ADC accuracy. ...
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Capacitive Touch Characteristics 7.9.9.1 Discharge Current Source Table 7-34. DICS Characteristics Symbol Parameter R Internal resistor REF k Trim step size 7.9.9.2 Strong Pull-up Pull-down Table 7-35. Strong Pull-up Pull-down Parameter Pull-down resistor Pull-up resistor 32099G–06/2011 AT32UC3L016/32/64 Min Typ ...
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Timing Characteristics 7.10.1 Startup, Reset, and Wake-up Timing The startup, reset, and wake-up timings are calculated using the following formula CONST Where another clock source than RCSYS is selected as CPU clock the startup time of ...
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USART in SPI Mode Timing 7.10.3.1 Master mode Figure 7-8. SPCK MISO MOSI Figure 7-9. SPCK MISO MOSI Table 7-38. USART in SPI Mode Timing, Master Mode Symbol Parameter USPI0 MISO setup time before SPCK rises USPI1 MISO hold ...
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Maximum SPI Frequency, Master Output The maximum SPI master output frequency is given by the following formula: Where the maximum frequency of the SPI pins. Please refer to the I/O Pin Characteristics section for the maximum frequency of the pins. ...
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Figure 7-12. USART in SPI Slave Mode NPCS Timing SPCK, CPOL=0 SPCK, CPOL=1 NSS Table 7-39. USART in SPI mode Timing, Slave Mode Symbol Parameter USPI6 SPCK falling to MISO delay USPI7 MOSI setup time before SPCK rises USPI8 MOSI ...
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The maximum SPI slave output frequency is given by the following formula: Where the SPI master setup time. Please refer to the SPI master datasheet for maximum frequency of the CLK_SPI. Refer to the SPI chapter for a description of ...
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Table 7-40. SPI Timing, Master Mode Symbol Parameter SPI0 MISO setup time before SPCK rises SPI1 MISO hold time after SPCK rises SPI2 SPCK rising to MOSI delay SPI3 MISO setup time before SPCK falls SPI4 MISO hold time after ...
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Figure 7-16. SPI Slave Mode With (CPOL= NCPHA (CPOL= NCPHA= 1) SPCK MISO MOSI Figure 7-17. SPCK, CPOL=0 SPCK, CPOL=1 NPCS Table 7-41. SPI Timing, Slave Mode Symbol Parameter SPI6 SPCK falling to MISO delay SPI7 MOSI setup ...
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The maximum SPI slave input frequency is given by the following formula: Where CPOL and NCPHA. ter for a description of this clock. Maximum SPI Frequency, Slave Output Mode The maximum SPI slave output frequency is given by the following ...
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Table 7-42. TWI-Bus Timing Requirements Symbol Parameter t Data set-up time SU-DAT-TWI t SU-DAT t TWCK LOW period LOW-TWI t LOW t TWCK HIGH period HIGH f TWCK frequency TWCK ≤ f Notes: 1. Standard mode: TWCK 2. A device ...
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JTAG Timing Figure 7-18. JTAG Interface Signals TMS/TDI Boundary Scan Inputs Boundary Scan Outputs (1) Table 7-43. JTAG Timings Symbol Parameter JTAG0 TCK Low Half-period JTAG1 TCK High Half-period JTAG2 TCK Period JTAG3 TDI, TMS Setup before TCK High ...
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Mechanical Characteristics 8.1 Thermal Considerations 8.1.1 Thermal Data Table 8-1 Table 8-1. Symbol θ JA θ JC θ JA θ JC θ JA θ JC 8.1.2 Junction Temperature The average chip-junction temperature where: • ...
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Package Drawings Figure 8-1. TQFP-48 Package Drawing Table 8-2. Device and Package Maximum Weight 140 Table 8-3. Package Characteristics Moisture Sensitivity Level Table 8-4. Package Reference JEDEC Drawing Reference JESD97 Classification 32099G–06/2011 AT32UC3L016/32/64 mg MSL3 MS-026 E3 74 ...
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Figure 8-2. QFN-48 Package Drawing Note: The exposed pad is not connected to anything. Table 8-5. Device and Package Maximum Weight 140 Table 8-6. Package Characteristics Moisture Sensitivity Level Table 8-7. Package Reference JEDEC Drawing Reference JESD97 Classification 32099G–06/2011 AT32UC3L016/32/64 ...
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Figure 8-3. TLLGA-48 Package Drawing Table 8-8. Device and Package Maximum Weight 39.3 Table 8-9. Package Characteristics Moisture Sensitivity Level Table 8-10. Package Reference JEDEC Drawing Reference JESD97 Classification 32099G–06/2011 AT32UC3L016/32/64 mg MSL3 N ...
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Soldering Profile Table 8-11 Table 8-11. Profile Feature Average Ramp-up Rate (217°C to Peak) Preheat Temperature 175°C ±25°C Time Maintained Above 217°C Time within 5°C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25°C to Peak Temperature ...
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... Ordering Information Table 9-1. Ordering Information Device Ordering Code AT32UC3L064-AUTES AT32UC3L064-AUT AT32UC3L064-AUR AT32UC3L064-ZAUES AT32UC3L064 AT32UC3L064-ZAUT AT32UC3L064-ZAUR AT32UC3L064-D3HES AT32UC3L064-D3HT AT32UC3L064-D3HR AT32UC3L032-AUT AT32UC3L032-AUR AT32UC3L032-ZAUT AT32UC3L032 AT32UC3L032-ZAUR AT32UC3L032-D3HT AT32UC3L032-D3HR AT32UC3L016-AUT AT32UC3L016-AUR AT32UC3L016-ZAUT AT32UC3L016 AT32UC3L016-ZAUR AT32UC3L016-D3HT AT32UC3L016-D3HR 32099G–06/2011 Carrier Type Package Package Type ES Tray TQFP 48 Tape & ...
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Errata 10.1 Rev. E 10.1.1 Processor and Architecture Hardware breakpoints may corrupt MAC results Hardware breakpoints on MAC instructions may corrupt the destination register of the MAC instruction. Fix/Workaround Place breakpoints on earlier or later instructions. Privilege violation when ...
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If the CPU is in idle or frozen sleep mode and a module state that triggers sleep walk- ing, all PB clocks will be masked except the PB clock to the sleepwalking module. Fix/Workaround Mask all clock ...
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WDT Clearing the Watchdog Timer (WDT) counter in second half of timeout period will issue a Watchdog reset If the WDT counter is cleared in the second half of the timeout period, the WDT will immedi- ately issue a ...
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Fix/Workaround Always disable mode fault detection before using the SPI by writing a one to MR.MODFDIS. SPI RDR.PCS is not correct The PCS (Peripheral Chip Select) field in the SPI RDR (Receive Data Register) does not correctly indicate the ...
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Ensure that duty cycle writes from the user interface are not performed in a PWMA period when an incoming peripheral event is expected. 10.1.10 ADCIFB Using STARTUPTIME larger than 0x1F will freeze the ADC Writing a value larger than 0x1F ...
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Solution 1: Disable OSC0 by writing a zero to the Oscillator Enable bit in the System Control Interface (SCIF) Oscillator Control Register (SCIF.OSC0CTRL.OSCEN) before going to a sleep mode where OSC0 is disabled. Solution 2: Pull down or up XIN0 ...
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Before going to sleep modes where RCSYS is stopped, make sure the division factor between CPU/HSB and PBx frequencies is less than or equal to 4. External reset in Shutdown mode If an external reset is asserted while the device ...
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Wait for 32 reference clock cycles after the tuner is enabled, then read the FLO.NOLOCK bit to check set set, a lock can not be obtained for this configuration of reference clock and target ...
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GPIO Clearing GPIO interrupt may fail Writing a one to the GPIO.IFRC register to clear an interrupt will be ignored if interrupt is enabled for the corresponding port. Fix/Workaround Disable the interrupt, clear it by writing a one to ...
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TWI TWIM SR.IDLE goes high immediately when NAK is received When a NAK is received and there is a non-zero number of bytes to be transmitted, SR.IDLE goes high immediately and does not wait for the STOP condition to ...
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CAT CAT asynchronous wake will be delayed by one AST event period If the CAT detects a condition the should asynchronously wake the device in static mode, the asynchronous wake will not occur until the next AST event. For ...
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Solution 1: Disable OSC0 by writing a zero to the Oscillator Enable bit in the System Control Interface (SCIF) Oscillator Control Register (SCIF.OSC0CTRL.OSCEN) before going to a sleep mode where OSC0 is disabled. Solution 2: Pull down or up XIN0 ...
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Transfer error will stall a transmit peripheral handshake interface If a transfer error is encountered on a channel transmitting to a peripheral, the peripheral handshake of the active channel will stall and the PDCA will not do any more transfers ...
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Fix/Workaround None. Open Mode is not functional The Open Mode is not functional. Fix/Workaround None. VERSION register reads 0x100 The VERSION register reads 0x100 instead of 0x110. Fix/Workaround None. 10.4.5 HMATRIX In the PRAS and PRBS registers, the MxPR fields ...
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None. Clock sources will not be stopped in Static mode if the difference between CPU and PBx division factor is larger than 4 If the division factor between the CPU/HSB and PBx frequencies is more than 4 when enter- ing ...
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Writing to ICR masks any new SCIF interrupt received in the same clock cycle, regardless of write value. Fix/Workaround For every interrupt except BODDET, SM33DET, and VREGOK the PCLKSR register can be read to detect new interrupts. BODDET, SM33DET and ...
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The DFLLIF dithering does not work. Fix/Workaround None. DFLLIF might lose fine lock when dithering is disabled When dithering is disabled and fine lock has been acquired, the DFLL might lose the fine lock resulting 20% over-/undershoot. ...
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OSC32VERSION register reads 0x100 instead of 0x101. Fix/Workaround None. VREGVERSION register reads 0x100 VREGVERSION register reads 0x100 instead of 0x101. Fix/Workaround None. RC120MVERSION register reads 0x100 RC120MVERSION register reads 0x100 instead of 0x101. Fix/Workaround None. 10.4.8 AST AST wake signal ...
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Fix/Workaround None. GCLK5 can not be used as source for the CLK_MSR The frequency for GCLK5 can not be measured by the FREQM. Fix/Workaround None. 10.4.11 GPIO GPIO interrupt can not be cleared when interrupts are disabled The GPIO interrupt ...
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Fix/Workaround Read the last received data, then perform a software reset by writing a one to the Software Reset bit in the Control Register (CR.SWRST). SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and NCPHA=0 When multiple ...
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Enable the TWIM first and then enable the TWD and TWCK peripheral pins in the GPIO controller necessary to disable the TWIM, first disable the TWD and TWCK peripheral pins in the GPIO controller and then disable ...
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The duty cycle registers will be corrupted if written when the timebase counter overflows. If the duty cycle registers are written exactly when the timebase counter overflows at TOP, the duty cycle registers may become corrupted. Fix/Workaround Write to the ...
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Writing a value larger than 0x1F to the Startup Time field in the ADC Configuration Register (ACR.STARTUP) will freeze the ADC, and the Busy Status bit in the Status Register (SR.BUSY) will never be cleared. Fix/Workaround Do not write values ...
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DISHIFT field is stuck at zero The DISHIFT field in the MGCFG1, TGACFG1, TGBCFG1, and ATCFG1 registers is stuck at zero and cannot be written to a different value. Capacitor discharge time will only be determined by the DILEN field. ...
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Static mode. Fix/Workaround None. aWire CPU clock speed robustness The aWire memory speed request command counter warps at clock speeds below approxi- mately 5kHz. Fix/Workaround None. The aWire debug interface is reset after leaving ...
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Fix/Workaround Solution 1: Disable OSC0 by writing a zero to the Oscillator Enable bit in the System Control Interface (SCIF) Oscillator Control Register (SCIF.OSC0CTRL.OSCEN) before going to a sleep mode where OSC0 is disabled. Solution 2: Pull down or up ...
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Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 11.1 Rev 06/2011 ...
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... Added pin capacitance, rise, and fall times. Added timing characteristics. Removed all TBDs. Added ADC analog input characteristics. Symbol cleanup. Errata: Updated errata list. Ordering Information: Ordering code for TQFP ES changed from AT32UC3L064-AUES to AT32UC3L064-AUTES. TLLGA48 Tray option added. Features and Description: Added QTouch library support. ...
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Rev. A – 06/2009 1. 32099G–06/2011 SCIF: Temperature sensor is connected to ADC channel 9, not 7. SCIF: Updated the oscillator connection figure for OSC0 GPIO: ...
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Table of Contents Features ..................................................................................................... 1 1 Description ............................................................................................... 3 2 Overview ................................................................................................... 5 3 Package and Pinout ................................................................................. 7 4 Processor and Architecture .................................................................. 18 5 Memories ................................................................................................ 32 6 Supply and Startup Considerations ..................................................... 36 7 Electrical Characteristics ...
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Mechanical Characteristics ................................................................... 73 9 Ordering Information ............................................................................. 78 10 Errata ....................................................................................................... 79 11 Datasheet Revision History ................................................................ 105 Table of Contents....................................................................................... i 32099G–06/2011 7.8 Flash Characteristics .......................................................................................54 7.9 Analog Characteristics .....................................................................................55 7.10 Timing Characteristics .....................................................................................63 8.1 Thermal Considerations ...
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