AT86RF212 Atmel Corporation, AT86RF212 Datasheet - Page 105
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AT86RF212
Manufacturer Part Number
AT86RF212
Description
Manufacturer
Atmel Corporation
Specifications of AT86RF212
Max. Operating Frequency
0 MHz
Crypto Engine
AES
Operating Voltage (vcc)
1.8 to 3.6
Frequency Band
700/800/900MHz
Max Data Rate (mb/s)
1
Antenna Diversity
No
External Pa Control
Yes
Power Output (dbm)
10
Receiver Sensitivity (dbm)
-110
Receive Current Consumption (ma)
9.0
Transmit Current Consumption (ma)
18 at 5dBm
Link Budget (dbm)
120
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7.3.6 Register Description
8168C-MCU Wireless-02/10
Register 0x16 (RF_CTRL_0):
This register contains control signals to configure the transmit path.
Table 7-10. Register 0x16 (RF_CTRL_0)
• Bit 7:6 – PA_LT
These register bits control the lead time of the PA enable signal relative to the TX data
start, see Figure 7-9. This allows to enable the PA 2, 4, 6, or 8 µs before the transmit
signal starts. The PA enable signal can also be output at pin DIG3/DIG4 to provide a
control signal for an external RF front-end; for details, refer to section 9.4.
Table 7-11. PA Enable Time Relative to the TX start
Setting of PA_LT is only effective in TRX_OFF, PLL_ON, and TX_ARET_ON mode.
• Bit 5:2 – Reserved
• Bit 1:0 – GC_TX_OFFS
These register bits provide an offset between the TX power control word TX_PWR
(register 0x05, PHY_TX_PWR) and the actual TX power. This 2-bit word is added to the
TX power control word before it is applied to the circuit block which adjusts the TX
power. It can be used to compensate differences of the average TX power depending of
the modulation format, see Table 7-16 .
Table 7-12. TX Power Offset
Register 0x05 (PHY_TX_PWR):
This register controls the transmitter output power.
Bit
Name
Read/Write
Reset Value
Bit
Name
Read/Write
Reset Value
Register Bits
PA_LT
Register Bits
GC_TX_OFFS
7
PA_LT[1]
R/W
0
3
Reserved
R
0
Value
Value
0
1
2
3
0
1
2
3
6
PA_LT[0]
R/W
0
2
Reserved
R
0
PA Enable Lead Time [μs]
5
Reserved
R/W
1
1
GC_TX_OFFS[1]
R/W
0
TX Power Offset [dB]
+1
+2
2
4
6
8
-1
0
AT86RF212
4
Reserved
R/W
1
0
GC_TX_OFFS[0]
R/W
1
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