AT86RF212 Atmel Corporation, AT86RF212 Datasheet - Page 62
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AT86RF212
Manufacturer Part Number
AT86RF212
Description
Manufacturer
Atmel Corporation
Specifications of AT86RF212
Max. Operating Frequency
0 MHz
Crypto Engine
AES
Operating Voltage (vcc)
1.8 to 3.6
Frequency Band
700/800/900MHz
Max Data Rate (mb/s)
1
Antenna Diversity
No
External Pa Control
Yes
Power Output (dbm)
10
Receiver Sensitivity (dbm)
-110
Receive Current Consumption (ma)
9.0
Transmit Current Consumption (ma)
18 at 5dBm
Link Budget (dbm)
120
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62
AT86RF212
• Bit 7 – PA_EXT_EN
Refer to section 9.4.3.
• Bit 6 – IRQ_2_EXT_EN
Refer to section 9.5.2.
• Bit 5 – TX_AUTO_CRC_ON
If set, register bit TX_AUTO_CRC_ON enables the automatic FCS generation. For
further details refer to section 6.3.
• Bit 4 – RX_BL_CTRL
Refer to section 9.6.2.
• Bit 3:2 – SPI_CMD_MODE
Refer to section 4.4.1.
• Bit 1:0 – IRQ_MASK_MODE, IRQ_POLARITY
Refer to section 4.7.2.
Register 0x17 (XAH_CTRL_1):
The XAH_CTRL_1 register is a control register for Extended Operating Mode.
Table 5-23. Register 0x17 (XAH_CTRL_1)
• Bit 7 – Reserved
• Bit 6 – CSMA_LBT_MODE
Refer to section 6.7.3.
• Bit 5 – AACK_FLTR_RES_FT
This register bit shall only be set if AACK_UPLD_RES_FT = 1.
If AACK_FLTR_RES_FT = 1, reserved frame types are filtered like data frames as
specified
IEEE 802.15.4-2006, section 7.2.1.1.1. Interrupt IRQ_5 (AMI) is issued upon passing
the frame filter, see section 6.2.
Bit
Name
Read/Write
Reset Value
Bit
Name
Read/Write
Reset Value
Bit
Name
Read/Write
Reset Value
in
3
SPI_CMD_MODE
R/W
0
7
Reserved
R/W
0
3
Reserved
R
0
IEEE 802.15.4-2006.
2
SPI_CMD_MODE
R/W
0
6
CSMA_LBT_MODE
R/W
0
2
AACK_ACK_TIME
R/W
0
Reserved
1
IRQ_MASK_MODE
R/W
0
5
AACK_FLTR_RES_FT
R/W
0
1
AACK_PROM_MODE
R/W
0
frame
types
are
8168C-MCU Wireless-02/10
0
IRQ_POLARITY
R/W
0
4
AACK_UPLD_RES_FT
R/W
0
0
Reserved
R
0
explained
in