AT86RF212 Atmel Corporation, AT86RF212 Datasheet - Page 127

• Manufacturer Part Number: AT86RF212
• Manufacturer: Atmel Corporation

Specifications of AT86RF212

• Max. Operating Frequency: 0 MHz
• Crypto Engine: AES
• Operating Voltage (vcc): 1.8 to 3.6
• Frequency Band: 700/800/900MHz
• Max Data Rate (mb/s): 1
• Antenna Diversity: No
• External Pa Control: Yes
• Power Output (dbm): 10
• Receiver Sensitivity (dbm): -110
• Receive Current Consumption (ma): 9.0
• Transmit Current Consumption (ma): 18 at 5dBm
• Link Budget (dbm): 120

8168C-MCU Wireless-02/10
Register 0x1A (PLL_CF):
This register controls the operation of the center frequency calibration loop.
Table 7-40. Register 0x1A (PLL_CF)
• Bit 7 – PLL_CF_START
PLL_CF_START = 1 initiates the center frequency calibration. When the calibration
cycle has finished after at most 25 µs, the register bit PLL_CF_START is reset to 0.
• Bit 6:5
These bits are reserved and must always be written back using the reset values.
• Bit 4:0 – PLL_CF
Bits 4:0 represent the current CF state of the PLL. In order to assure the shortest
possible calibration time, they should not be changed when starting center frequency
tuning.
Register 0x1B (PLL_DCU):
This register controls the operation of the delay cell calibration loop.
Table 7-41. Register 0x1B (PLL_DCU)
• Bit 7 – PLL_DCU_START
PLL_DCU_START = 1 initiates the delay cell calibration. The calibration cycle is
completed after 10 µs and the register bit PLL_DCU_START is set to 0. The register bit
is cleared immediately after finishing the calibration.
• Bit 6:0 – Reserved
Bit
Name
Read/Write
Reset Value
Bit
Name
Read/Write
Reset Value
Bit
Name
Read/Write
Reset Value
Bit
Name
Read/Write
Reset Value
7
PLL_CF_START
R/W
0
3
PLL_CF[3]
R/W
1
7
PLL_DCU_START
R/W
0
3
Reserved
R/W
0
6
Reserved
R/W
1
2
PLL_CF[2]
R/W
0
6
Reserved
R/W
1
2
Reserved
R/W
0
5
Reserved
R/W
0
1
PLL_CF[1]
R/W
0
5
Reserved
R/W
0
1
Reserved
R/W
0
AT86RF212
4
PLL_CF[4]
R/W
0
0
PLL_CF[0]
R/W
0
4
Reserved
R/W
0
0
Reserved
R/W
0
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