AT89C5131A-L Atmel Corporation, AT89C5131A-L Datasheet - Page 134
AT89C5131A-L
Manufacturer Part Number
AT89C5131A-L
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT89C5130A-M.pdf
(34 pages)
2.AT89C5131A-L.pdf
(4 pages)
3.AT89C5131A-L.pdf
(186 pages)
Specifications of AT89C5131A-L
Flash (kbytes)
32 Kbytes
Max. Operating Frequency
48 MHz
Cpu
8051-12C
Max I/o Pins
34
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
1
Sram (kbytes)
1.25
Eeprom (bytes)
1024
Self Program Memory
API
Operating Voltage (vcc)
3.0 to 3.6
Timers
4
Isp
UART/USB
Watchdog
Yes
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USB Interrupt Control System
134
AT89C5131A-L
Table 91. Priority Levels
As shown in Figure 71, many events can produce a USB interrupt:
•
•
•
•
•
•
•
•
TXCMPL: Transmitted In Data (see Table 98 on page 141). This bit is set by
hardware when the Host accept a In packet.
RXOUTB0: Received Out Data Bank 0 (see Table 98 on page 141). This bit is set
by hardware when an Out packet is accepted by the endpoint and stored in bank 0.
RXOUTB1: Received Out Data Bank 1 (only for Ping-pong endpoints) (see Table 98
on page 141). This bit is set by hardware when an Out packet is accepted by the
endpoint and stored in bank 1.
RXSETUP: Received Setup (see Table 98 on page 141). This bit is set by hardware
when an SETUP packet is accepted by the endpoint.
STLCRC: STALLED (only for Control, Bulk and Interrupt endpoints) (see Table 98
on page 141). This bit is set by hardware when a STALL handshake has been sent
as requested by STALLRQ, and is reset by hardware when a SETUP packet is
received.
SOFINT: Start of Frame Interrupt (See “USBIEN Register USBIEN (S:BEh) USB
Global Interrupt Enable Register” on page 138.). This bit is set by hardware when a
USB Start of Frame packet has been received.
WUPCPU: Wake-Up CPU Interrupt (See “USBIEN Register USBIEN (S:BEh) USB
Global Interrupt Enable Register” on page 138.). This bit is set by hardware when a
USB resume is detected on the USB bus, after a SUSPEND state.
SPINT: Suspend Interrupt (See “USBIEN Register USBIEN (S:BEh) USB Global
Interrupt Enable Register” on page 138.). This bit is set by hardware when a USB
suspend is detected on the USB bus.
IPHUSB
0
0
1
1
IPLUSB
0
1
0
1
USB Priority Level
0
1
2
3
Lowest
Highest
4338F–USB–08/07
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