AT89C5131A-L Atmel Corporation, AT89C5131A-L Datasheet - Page 17

• Manufacturer Part Number: AT89C5131A-L
• Manufacturer: Atmel Corporation

Specifications of AT89C5131A-L

• Flash (kbytes): 32 Kbytes
• Max. Operating Frequency: 48 MHz
• Cpu: 8051-12C
• Max I/o Pins: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Sram (kbytes): 1.25
• Eeprom (bytes): 1024
• Self Program Memory: API
• Operating Voltage (vcc): 3.0 to 3.6
• Timers: 4
• Isp: UART/USB
• Watchdog: Yes

4338F–USB–08/07
Table 15. CKCON1 (S:AFh)
Clock Control Register 1
Reset Value = 0000 0000b
Table 16. PLLCON (S:A3h)
PLL Control Register
Reset Value = 0000 0000b
Table 17. PLLDIV (S:A4h)
PLL Divider Register
Reset Value = 0000 0000
Bit Number
Bit Number
Bit Number
R3
7-1
7-3
7-4
3-0
7
7
7
-
-
0
2
1
0
Mnemonic Description
Mnemonic Description
Mnemonic Description
PLOCK
PLLEN
EXT48
SPIX2
R3:0
N3:0
Bit
Bit
R2
Bit
6
6
6
-
-
-
-
Reserved
The value read from this bit is always 0. Do not set this bit.
SPI Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low,
this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Reserved
The value read from this bit is always 0. Do not set this bit.
External 48 MHz Enable Bit
Set this bit to bypass the PLL and disable the crystal oscillator.
Clear this bit to select the PLL output as USB clock and to enable the crystal
oscillator.
PLL Enable Bit
Set to enable the PLL.
Clear to disable the PLL.
PLL Lock Indicator
Set by hardware when PLL is locked.
Clear by hardware when PLL is unlocked.
PLL R Divider Bits
PLL N Divider Bits
R1
5
5
5
-
-
R0
4
4
4
-
-
N3
3
3
3
-
-
EXT48
N2
2
2
2
-
PLLEN
N1
1
1
1
-
PLOCK
SPIX2
N0
0
0
0
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