AT89C5131A-L Atmel Corporation, AT89C5131A-L Datasheet - Page 155
AT89C5131A-L
Manufacturer Part Number
AT89C5131A-L
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT89C5130A-M.pdf
(34 pages)
2.AT89C5131A-L.pdf
(4 pages)
3.AT89C5131A-L.pdf
(186 pages)
Specifications of AT89C5131A-L
Flash (kbytes)
32 Kbytes
Max. Operating Frequency
48 MHz
Cpu
8051-12C
Max I/o Pins
34
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
1
Sram (kbytes)
1.25
Eeprom (bytes)
1024
Self Program Memory
API
Operating Voltage (vcc)
3.0 to 3.6
Timers
4
Isp
UART/USB
Watchdog
Yes
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Hardware Watchdog
Timer
Using the WDT
4338F–USB–08/07
The WDT is intended as a recovery method in situations where the CPU may be sub-
jected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer
ReSeT (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable
the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location
0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator
is running and there is no way to disable the WDT except through reset (either hardware
reset or WDT overflow reset). When WDT overflows, it will drive an output RESET LOW
pulse at the RST-pin.
To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR
location 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH
and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it
reaches 16383 (3FFFH) and this will reset the device. When WDT is enabled, it will
increment every machine cycle while the oscillator is running. This means the user must
reset the WDT at least every 16383 machine cycle. To reset the WDT the user must
write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The WDT counter
cannot be read or written. When WDT overflows, it will generate an output RESET pulse
at the RST-pin. The RESET pulse duration is 96 x T
1/F
of code that will periodically be executed within the time required to prevent a WDT
reset.
To have a more powerful WDT, a 2
capability, ranking from 16 ms to 2s at F
WDTPRG register description, Table 110.
Table 109. WDTRST Register
WDTRST - Watchdog Reset Register (0A6h)
Reset Value = XXXX XXXXb
Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in
sequence.
CLK PERIPH
7
-
. To make the best use of the WDT, it should be serviced in those sections
6
-
5
-
7
4
-
counter has been added to extend the Time-out
OSCA
= 12 MHz. To manage this feature, refer to
3
-
CLK PERIPH
2
-
, where T
1
-
CLK PERIPH
0
-
155
=
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