AT89C5131A-L Atmel Corporation, AT89C5131A-L Datasheet - Page 94

• Manufacturer Part Number: AT89C5131A-L
• Manufacturer: Atmel Corporation

Specifications of AT89C5131A-L

• Flash (kbytes): 32 Kbytes
• Max. Operating Frequency: 48 MHz
• Cpu: 8051-12C
• Max I/o Pins: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Sram (kbytes): 1.25
• Eeprom (bytes): 1024
• Self Program Memory: API
• Operating Voltage (vcc): 3.0 to 3.6
• Timers: 4
• Isp: UART/USB
• Watchdog: Yes

Figure 45. Data Transmission Format (CPHA = 0)
Figure 46. Data Transmission Format (CPHA = 1)
Figure 47. CPHA/SS Timing
94
AT89C5131A-L
MOSI (from Master)
SCK cycle number
MISO (from Slave)
MOSI (from Master)
SCK (CPOL = 0)
SCK (CPOL = 1)
MISO (from Slave)
SCK cycle number
SPEN (internal)
SCK (CPOL = 0)
SCK (CPOL = 1)
Capture point
SPEN (internal)
SS (to Slave)
Capture point
SS (to Slave)
MISO/MOSI
(CPHA = 0)
(CPHA = 1)
Master SS
Slave SS
Slave SS
As shown in Figure 46, the first SCK edge is the MSB capture strobe. Therefore the
Slave must begin driving its data before the first SCK edge, and a falling edge on the SS
pin is used to start the transmission. The SS pin must be toggled high and then low
between each byte transmitted (Figure 43).
Figure 47 shows an SPI transmission in which CPHA is’1’. In this case, the Master
begins driving its MOSI pin on the first SCK edge. Therefore the Slave uses the first
SCK edge as a start transmission signal. The SS pin can remain low between transmis-
sions (Figure 42). This format may be preferable in systems having only one Master and
only one Slave driving the MISO data line.
MSB
MSB
MSB
1
MSB
1
2
bit6
bit6
2
bit6
bit6
Byte 1
3
bit5
bit5
3
bit5
bit5
bit4
bit4
4
bit4
bit4
4
Byte 2
bit3
bit3
5
bit3
bit3
5
6
bit2
bit2
6
bit2
bit2
Byte 3
7
bit1
bit1
7
bit1
bit1
LSB
8
8
LSB
LSB
LSB
4338F–USB–08/07