AT89LP51 Atmel Corporation, AT89LP51 Datasheet - Page 13

• Manufacturer Part Number: AT89LP51
• Manufacturer: Atmel Corporation

Specifications of AT89LP51

• Flash (kbytes): 4 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 36
• Uart: 1
• Sram (kbytes): 0.25
• Eeprom (bytes): 256
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 3
• Isp: SPI
• Watchdog: Yes

3.1.2
3709D–MICRO–12/11
SIG
Figure 3-3.
In order for Fast mode to fetch externally, two wait states must be inserted for every clock cycle,
increasing the instruction execution time by a factor of 3. However, due to other optimizations,
external Fast mode instructions may still be 1/4 to 1/2 faster than their Compatibility mode equiv-
alents. Note that if ALE is allowed to toggle in Fast mode, there is a possibility that when the
CPU jumps from internal to external execution a short pulse may occur on ALE as shown in
ure
this behavior can be avoided by setting the DISALE bit prior to any jump above the 8K border.
Figure 3-4.
In addition to the 64K code space, the AT89LP51/52 also supports a 256-byte User Signature
Array and a 128-byte Atmel Signature Array that are accessible by the CPU. The Atmel Signa-
ture Array is initialized with the Device ID in the factory. The User Signature Array is available for
user identification codes or constant parameter data. Data stored in the signature array is not
secure. Security bits will disable writes to the array; however, reads by an external device pro-
grammer are always allowed.
In order to read from the signature arrays, the SIGEN bit (AUXR1.3) must be set (See
on page
User Signature Array is mapped from addresses 0100h to 01FFh and the Atmel Signature Array
is mapped from addresses 0000h to 007Fh. SIGEN must be cleared before using MOVC to
3-4. The setup time from the address to the falling edge of ALE remains the same. However,
DISALE=0
DISALE=1
PSEN
PSEN
28). While SIGEN is one, MOVC A,@A+DPTR will access the signature arrays. The
CLK
ALE
CLK
ALE
ALE
P0
P2
P0
P2
External Program Memory Fetches
Internal/External Program Memory Boundary (Fast Mode)
DATA
SAMPLED
INTERNAL EXECUTION
PCL
OUT
P0 SFR OUT
P2 SFR OUT
PCH OUT
FLOAT
DATA
SAMPLED
PCL OUT
OUT
PCL
SHORT
PULSE
PCH OUT
PCH OUT
FLOAT
EXTERNAL EXECUTION
AT89LP51/52
DATA
SAMPLED
DATA
SAMPLED
PCL OUT
OUT
PCL
PCH OUT
PCH OUT
Table 5-3
Fig-
13