AT89LP51 Atmel Corporation, AT89LP51 Datasheet - Page 9

• Manufacturer Part Number: AT89LP51
• Manufacturer: Atmel Corporation

Specifications of AT89LP51

• Flash (kbytes): 4 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 36
• Uart: 1
• Sram (kbytes): 0.25
• Eeprom (bytes): 256
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 3
• Isp: SPI
• Watchdog: Yes

2.3.1
2.3.2
2.3.3
2.3.4
3709D–MICRO–12/11
Instruction Execution
System Clock
Reset
Timer/Counters
In Compatibility mode the AT89LP51/52 CPU uses the six-state machine cycle of the standard
8051 where instruction bytes are fetched every three system clock cycles. Execution times in
this mode are identical to AT89S51/52. For greater performance the user can enable Fast mode
by disabling the Compatibility fuse. In Fast mode the CPU fetches one code byte from memory
every clock cycle instead of every three clock cycles. This greatly increases the throughput of
the CPU. Each standard instruction executes in only 1 to 4 clock cycles. See
Summary” on page 75
operations may need to be retuned to achieve the desired results in Fast mode.
By default in Compatibility mode the system clock frequency is divided by 2 from the externally
supplied XTAL1 frequency for compatibility with standard 8051s (12 clocks per machine cycle).
The System Clock Divider can scale the system clock versus the oscillator source (See
6.4 on page
cycle) or the clock may be further divided to reduce the operating frequency. In Fast mode the
clock divider defaults to divide by 1.
The system clock source is selectable between the crystal oscillator, an externally driven clock
and an internal 1.8432 MHz auxiliary oscillator. See
figuration Fuses” on page
The RST pin of the AT89LP51/52 has selectable polarity using the POL pin (formerly EA). When
POL is high the RST pin is active high with a pull-down resistor and when POL is low the RST
pin is active low with a pull-up resistor. For existing AT89S51/52 sockets where EA is tied to
VDD, replacing AT89S51/52 with AT89LP51/52 will maintain the active high reset. Note that
forcing external execution by tying EA low is not supported.
The AT89LP51/52 includes an on-chip Power-On Reset and Brown-out Detector circuit that
ensures that the device is reset from system power up. In most cases a RC startup circuit is not
required on the RST pin, reducing system cost, and the RST pin may be left unconnected if a
board-level reset is not present.
A common prescaler is available to divide the time base for Timer 0, Timer 1, Timer 2 and the
WDT. The TPS
Compatibility mode TPS
machine cycle. The counting rate can be adjusted linearly from the system clock rate to 1/16 of
the system clock rate by changing TPS
clock rate. TPS does not affect Timer 2 in Clock Out or Baud Generator modes.
In Compatibility mode the sampling of the external Timer/Counter pins: T0, T1, T2 and T2EX;
and the external interrupt pins, INT0 and INT1, is also controlled by the prescaler. In Fast mode
these pins are always sampled at the system clock rate.
Both Timer 0 and Timer 1 can toggle their respective counter pins, T0 and T1, when they over-
flow by setting the output enable bits in TCONB.
The Watchdog Timer includes a 7-bit prescaler for longer timeout periods than the AT89S51/52.
Note that in Fast Mode the WDIDLE and DISRTO bits are located in WDTCON and not in
AUXR.
31). The divide-by-2 can be disabled to operate in X2 mode (6 clocks per machine
3-0
bits in the CLKREG SFR control the prescaler
for more details. Any software delay loops or instruction-based timing
3-0
86.
defaults to 0101B, which causes the timers to count once every
3-0
. In Fast mode TPS
“System Clock” on page 29
3-0
defaults to 0000B, or the system
(Table 6-2 on page
AT89LP51/52
“Instruction Set
and
“User Con-
Section
31). In
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