AT89LP51 Atmel Corporation, AT89LP51 Datasheet - Page 41

• Manufacturer Part Number: AT89LP51
• Manufacturer: Atmel Corporation

Specifications of AT89LP51

• Flash (kbytes): 4 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 36
• Uart: 1
• Sram (kbytes): 0.25
• Eeprom (bytes): 256
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 3
• Isp: SPI
• Watchdog: Yes

10. I/O Ports
10.1
3709D–MICRO–12/11
Port Configuration
The AT89LP51/52 can be configured for between 32 and 36 I/O pins. The exact number of I/O
pins available depends on the clock, external memory and package type as shown in
1.
Table 10-1.
Each 8-bit port on the AT89LP51/52 may be configured in one of four modes: quasi-bidirectional
(standard 8051 port outputs), push-pull output, open-drain output, or input-only. Port modes may
be assigned in software on a port-by-port basis as shown in
listed in
(See
input-only mode after reset. When the fuse is disabled, all port pins on P1, P2 and P3 default to
quasi-bidirectional mode after reset and are weakly pulled high. P0 is set to Open-drain mode.
P4 always operates in quasi-bidirectional mode.
Each port pin also has a Schmitt-triggered input for improved input noise rejection. During
Power-down all the Schmitt-triggered inputs are disabled with the exception of P3.2 (INT0), P3.3
(INT1), RST, P4.6 (XTAL1) and P4.7 (XTAL2). Therefore, P3.2, P3.3, P4.6 and P4.7 should not
be left floating during Power-down.
.
Table 10-2.
Clock Source
External Crystal or
Resonator
External Clock
Internal RC
Oscillator
“User Configuration Fuses” on page
PxM0
0
0
1
1
Table
I/O Pin Configurations
Configuration Modes for Port x
10-3. The Tristate-Port User Fuse determines the default state of the port pins
External Program Access
PxM1
Yes (PSEN+ALE+P0+P2)
Yes (PSEN+ALE+P0+P2)
Yes (PSEN+ALE+P0+P2)
0
1
0
1
No
No
No
Port Mode
Quasi-bidirectional
Push-pull Output
Input Only (High Impedance)
Open-Drain Output
86). When the fuse is enabled, all port pins default to
Yes (ALE+RD+WR+P0)
Yes (ALE+RD+WR+P0)
Yes (ALE+RD+WR+P0)
External Data Access
Yes (RD+WR)
Yes (RD+WR)
Yes (RD+WR)
Table 10-2
No
No
No
No
No
No
AT89LP51/52
using the PMOD register
Number of I/O
Pins
14
16
31
34
15
17
32
35
16
18
33
36
Table 10-
41