AT89LP6440 Atmel Corporation, AT89LP6440 Datasheet
AT89LP6440
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AT89LP6440 Summary of contents
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... Input-Only (Tristate) • Push-pull CMOS Output • Open-drain • Operating Conditions – 2.4V to 3.6V V Voltage Range DD – -40° 85°C Temperature Range – MHz @ 2.4–3.6V ® 51 Products 8-bit Microcontroller with 32K/64K Bytes In-System Programmable Flash AT89LP3240 AT89LP6440 3706C–MICRO–2/11 ...
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Pin Configurations 1.1 40P6: 40-lead PDIP 1.2 44A: 44-lead TQFP (Top View) MOSI/P1.5 MISO/P1.6 SCK/P1.7 RST/P4.2 RXD/P3.0 TXD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 AT89LP3240/6440 2 T2/P1 VDD T2EX/P1 P0.0/AD0 SDA/P1 P0.1/AD1 SCL/P1 ...
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PLCC 1.4 44M1: 44-pad VQFN/MLF 3706C–MICRO–2/11 MOSI/P1.5 7 MISO/P1.6 8 SCK/P1.7 9 RST/P4.2 10 RXD/P3.0 11 VDD 12 TXD/P3.1 13 INT0/P3.2 14 INT1/P3.3 15 T0/P3.4 16 T1/P3.5 17 MOSI/P1.5 1 MISO/P1.6 2 SCK/P1.7 3 RST/P4.2 4 RXD/P3.0 ...
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Pin Description Table 1-1. AT89LP3240/6440 Pin Description Pin Number TQFP PLCC PDIP VQFN ...
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Table 1-1. AT89LP3240/6440 Pin Description Pin Number TQFP PLCC PDIP VQFN ...
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Table 1-1. AT89LP3240/6440 Pin Description Pin Number TQFP PLCC PDIP VQFN ...
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Timer 0 and Timer 1 in the AT89LP3240/6440 are enhanced with two new modes. Mode 0 can be configured as a variable 9- to 16-bit timer/counter and Mode 1 can be configured as a 16-bit auto-reload timer/counter. In addition, the ...
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System Configuration The AT89LP3240/6440 supports several system configuration options. Nonvolatile options are set through user fuses that must be programmed through the flash programming interface. Vola- tile options are controlled by software through individual bits of special function registers ...
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Comparison to Standard 8051 The AT89LP3240/6440 is part of a family of devices with enhanced features that are fully binary compatible with the 8051 instruction set. In addition, most SFR addresses, bit assignments, and pin alternate functions are identical ...
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There is no difference in counting rate between Timer 2’s Auto-Reload/Capture and Baud Rate/Clock Out modes. All modes increment the timer once per clock cycle. Timer 2 in Auto- Reload/Capture mode increments at 12 times the rate of standard 8051s. ...
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... On-chip Extra RAM and extended stack space On-chip nonvolatile Flash data memory External data memory On-chip nonvolatile Flash program memory (AT89LP3240) On-chip nonvolatile Flash program memory (AT89LP6440) On-chip nonvolatile Flash signature array 28). While SIGEN is one, MOVC A,@A+DPTR will access the signature arrays. The Section 3.5 on page 21) ...
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... UPPER BY INDIRECT 128 ADDRESSING ADDRESSING ONLY 80H 7FH DATA/IDATA ACCESSIBLE LOWER BY DIRECT 128 AND INDIRECT ADDRESSING 0 AT89LP6440 User Signature Array Atmel Signature Array Program Memory FFH SFR BY DIRECT 80H SPECIAL PORTS FUNCTION STATUS AND REGISTERS CONTROL BITS TIMERS REGISTERS STACK POINTER ACCUMULATOR (ETC ...
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IDATA The full 256 byte internal RAM can be indirectly addressed using the 8-bit pointers R0 and R1. The first 128 bytes of IDATA include the DATA space. The hardware stack is also located in the IDATA space when ...
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Some internal data memory spaces are mapped into portions of the XDATA address space. In this case the lower address ranges will access internal resources instead of external memory ...
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To enable write access to the nonvolatile data memory, the MWEN bit (MEMCON.4) must be set to one. When MWEN = 1 and DMEN = 1, MOVX @DPTR,A may be used to write to FDATA. FDATA uses flash memory with ...
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Figure 3-5. Figure 3-6. Frequently just a few bytes within a page must be updated while maintaining the state of the other bytes. There are two options for handling this situation that allow the Flash Data memory to emulate a ...
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Table 3-3. – Memory Control Register MEMCON MEMCON = 96H Not Bit Addressable IAP AERS Bit 7 6 Symbol Function IAP In-Application Programming Enable. When IAP = 1 and the IAP Fuse is enabled, programming of the CODE/SIG space is ...
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Figure 3-8 an 8-bit paged address. Port 0 serves as a multiplexed address/data bus to the RAM. The ALE strobe is used to latch the address byte into an external register so that Port 0 can be freed for data ...
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Port 0 configuration. The Port 0 configuration will determine the idle state of Port 0 when not accessing the external memory. Figure 3-9 respectively. The address on P0 and P2 is stable ...
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Figure 3-11. MOVX with One Wait State (WS = 01B) CLK ALE Figure 3-12. MOVX with Two Wait States (WS = 10B) CLK ALE Figure 3-13. MOVX with Three Wait ...
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SP for use with each stack space. Interrupts should be disabled while swapping copies such an application to prevent illegal stack accesses. All interrupt calls and PUSH, POP, ACALL, LCALL, RET and RETI ...
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Special Function Registers A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 4-1. See also Note that not all of the addresses are occupied, and unoccupied addresses may not be ...
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Enhanced CPU The AT89LP3240/6440 uses an enhanced 8051 CPU that runs times the speed of standard 8051 devices ( times the speed of X2 8051 devices). The increase in perfor- mance is ...
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Figure 5-3. Fetch Immediate Operand 5.1 Multiply–Accumulate Unit (MAC) The AT89LP3240/6440 includes a multiply and accumulate (MAC) unit that can significantly speed up many mathematical operations required for digital signal processing. The MAC unit includes a 16-by-16 bit multiplier and ...
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The MAC operation is performed by executing the MAC AB (A5 A4H) extended instruction. This two-byte instruction requires nine clock cycles to complete. The operand registers are not modi- fied by the instruction and the result is stored in the ...
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Table 5-1. – Digital Signal Processing Configuration Register DSPR DSPR = E2H Not Bit Addressable MRW1 MRW0 Bit 7 6 Symbol Function MRW M Register Window. Selects which pair of bytes from the 5-byte M register is accessible through MACH ...
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A summary of data pointer instructions with fast context switching is listed Table 5-2. Instruction JMP @A+DPTR MOV DPTR, #data16 MOV /DPTR, #data16 INC DPTR INC /DPTR MOVC A,@A+DPTR MOVC A,@A+/DPTR MOVX A,@DPTR MOVX A,@/DPTR MOVX @DPTR, A MOVX @/DPTR, ...
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Table 5-5. – Data Pointer Configuration Register DPCF DPCF = A2H Not Bit Addressable DPU1 DPU0 Bit 7 6 Symbol Function DPU1 Data Pointer 1 Update. When set, MOVX @DPTR and MOVC @DPTR instructions that use DPTR1 will also update ...
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Index Disable The MOVC Index Disable bit, MVCD (DSPR.1), disables the indexed addressing mode of the MOVC A, @A+DPTR instruction. When MVCD = 1, the MOVC instruction functions as MOVC A, @DPTR with no indexing as shown in routines ...
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Instruction Set Extensions Table 5-8 AT89LP3240/6440. For more information on the instruction set see Summary” on page “Instruction Set Extensions” on page Table 5-8. Opcode ...
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System Clock The system clock is generated directly from one of three selectable clock sources. The three sources are the on-chip crystal oscillator, external clock source, and internal RC oscillator. The on-chip crystal oscillator may also be configured for ...
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External Clock Source The external clock option disables the oscillator amplifier and allows XTAL1 to be driven directly by an external clock source as shown in general purpose I/O P4.1, or configured to output a divided version of the ...
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When CDV is updated, the new frequency will take affect within a maximum period of 128 x t Table 6-2. – Clock Control Register CLKREG CLKREG = 8FH Not Bit Addressable TPS3 TPS2 Bit 7 6 ...
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RST pin low longer than the time-out. Figure 7-1. Time-out Internal Internal If the Brown-out Detector (BOD) is also enabled, the start-up timer does not begin counting until ...
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The RST pin may be held low externally until these conditions are met. Table 7-1. SUT Fuse 1 7.2 Brown-out Reset The AT89LP3240/6440 has an ...
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Note: 7.4 Watchdog Reset When the Watchdog times out, it will generate an internal reset pulse lasting 16 clock cycles. Watchdog reset will also set the WDTOVF flag in WDTCON. To prevent a Watchdog reset, the watchdog reset sequence 1EH/E1H ...
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Table 8-1. – Power Control Register PCON PCON = 87H Not Bit Addressable SMOD1 SMOD0 Bit 7 6 Symbol Function SMOD1 Double Baud Rate bit. Doubles the baud rate of the UART in Modes SMOD0 ...
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Figure 8-1. PWD XTAL1 INT1 Internal Clock When PWDEX = “1”, the wake-up period is controlled externally by the interrupt. Again, at the falling edge on the interrupt pin, power-down is exited and the oscillator is restarted. However, the internal ...
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Figure 8-3. PWD XTAL1 RST Internal Clock Internal Reset 8.3.2 Analog Comparators The comparators will operate during Idle mode if enabled. To save power, the comparators should be disabled before entering Idle mode if possible. When the comparators are turned ...
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The IPxD bits located at the seventh bit of IP, IPH, IP2 and IP2H can be used to disable all inter- rupts of a given priority level, allowing software implementations of more complex interrupt priority handling schemes such as level-based ...
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Table 9-1. Interrupt System Reset External Interrupt 0 Timer 0 Overflow External Interrupt 1 Timer 1 Overflow Serial Port Interrupt Timer 2 Interrupt Analog Comparator Interrupt General-purpose Interrupt Compare/Capture Array Interrupt Serial Peripheral Interface Interrupt ADC Interrupt Two-Wire Interface Interrupt ...
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See Figure 9-1 Figure 9-1. Minimum Interrupt Response Time Clock Cycles 1 INT0 IE0 Ack. Instruction Cur. Instr. Figure 9-2. Maximum Interrupt ...
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Table 9-3. IE2 – Interrupt Enable 2 Register IE = B4H Not Bit Addressable – – Bit 7 6 Symbol Function ETWI Two-Wire Interface Interrupt Enable EADC ADC Interrupt Enable ESPI Serial Peripheral Interface Interrupt Enable ECC Compare/Capture Array Interrupt ...
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Symbol Function PSP Serial Peripheral Interface Interrupt Priority Low PCC Compare/Capture Array Interrupt Priority Low PGP General-purpose Interrupt 0 Priority Low Table 9-6. IPH – Interrupt Priority High Register IPH = B7H Not Bit Addressable PCH IP1D Bit 7 6 ...
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I/O Ports The AT89LP3240/6440 can be configured for between 35 and 38 I/O pins. The exact number of I/O pins available depends on the clock and reset options as shown in Table 10-1. Clock Source External Crystal or Resonator ...
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Quasi-bidirectional Output Port pins in quasi-bidirectional output mode function similar to standard 8051 port pins. A Quasi- bidirectional port can be used both as an input and output without the need to reconfigure the port. This is possible because ...
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Figure 10-3. Input Circuit for P3.2, P3.3, P4.0, P4.1 and P4.2 10.1.3 Open-drain Output The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port pin when the port latch contains a logic “0”. ...
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Port Analog Functions The AT89LP3240/6440 incorporates two analog comparators and an 8-channel analog-to-digital converter. In order to give the best analog performance and minimize power consumption, pins that are being used for analog functions must have both their digital ...
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Port Alternate Functions Most general-purpose digital I/O pins of the AT89LP3240/6440 share functionality with the vari- ous I/Os needed for the peripheral units. Alternate functions are connected to the pins in a logic AND fashion. In order to enable ...
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Table 10-6. Port Pin P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P4.2 P4.6 P4.7 AT89LP3240/6440 50 Port Pin Alternate Functions Configuration Bits PxM0.y PxM1.y P1M0.2 ...
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Enhanced Timer 0 and Timer 1 with PWM The AT89LP3240/6440 has two 16-bit Timer/Counters, Timer 0 and Timer 1, with the following features: • Two 16-bit timer/counters with 16-bit reload registers • Two independent 8-bit precision PWM outputs with ...
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Mode 0 – Variable Width Timer/Counter Both Timers in Mode 0 are 8-bit Counters with a variable prescaler. The prescaler may vary from bits depending on the PSC bits in TCONB, giving the timer a range ...
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Figure 11-2. Timer/Counter 1 Mode 1: 16-bit Auto-Reload INT1 Pin 11.3 Mode 2 – 8-bit Auto-Reload Timer/Counter Mode 2 configures the Timer register as an 8-bit Counter (TL1) with automatic reload, as shown in Figure TH1, which is preset by ...
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Mode 3 is for applications requiring an extra 8-bit timer or counter. With Timer 0 in Mode 3, the AT89LP3240/6440 can appear to have four Timer/Counters. When Timer Mode 3, Timer 1 can be turned on and ...
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Table 11-3. TMOD – Timer/Counter Mode Control Register TMOD Address = 089H Not Bit Addressable GATE1 C/T1 Bit 7 6 Symbol Function Timer 1 Gating Control. When set, Timer/Counter 1 is enabled only while INT1 pin is high and TR1 ...
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Table 11-4. – Timer/Counter Control Register B TCONB TCONB = 91H Not Bit Addressable PWM1EN PWM0EN Bit 7 6 Symbol Function PWM1EN Configures Timer 1 for Pulse Width Modulation output on T1 (P3.5). PWM0EN Configures Timer 0 for Pulse Width ...
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Mode 0 – 8-bit PWM with 8-bit Logarithmic Prescaler In Mode 0, TLx acts as a logarithmic prescaler driving 8-bit counter THx (see PSCx bits in TCONB control the prescaler value. On THx overflow, the duty cycle value in ...
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Figure 11-7. Timer/Counter 1 PWM Mode 1 GATE1 INT1 Pin Figure 11-8. Timer/Counter 1 PWM Mode 2 Note: Figure 11-9. PWM Mode 2 Waveform AT89LP3240/6440 58 ÷TPS OSC Control TR1 ÷TPS OSC Control TR1 GATE1 INT1 Pin {RH0 & RL0}/{RH1 ...
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Mode 3 – Split 8-bit PWM Timer 1 in PWM Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in PWM Mode 3 establishes TL0 and TH0 as two separate ...
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Enhanced Timer 2 The AT89LP3240/6440 includes a 16-bit Timer/Counter 2 with the following features: • 16-bit timer/counter with one 16-bit reload/capture register • One external reload/capture input • Up/Down counting mode with external direction control • UART baud rate ...
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Timer 2 Registers Control and status bits for Timer 2 are contained in registers T2CON (see T2MOD (see 16-bit timer register for Timer 2. The register pair {RCAP2H, RCAP2L} at addresses 0CBH and 0CAH are the 16-bit Capture/Reload register ...
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Symbol Function PHS [2-0] CCA Phase Mode. PWM channels may be grouped such that only one channel in a group produces a pulse in any one period. The PHS[2-0] bits may only be written when ...
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Figure 12-1. Timer 2 Diagram: Capture Mode OSC ÷TPS T2 PIN TRANSITION DETECTOR T2EX PIN 12.3 Auto-Reload Mode Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by ...
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RCAP2L and then overflows. The overflow sets TF2 and causes the timer registers to be reloaded with MIN. If EXEN2 = 1, a 1-to-0 transition on T2EX will clear the timer and set EXF2. The Timer 2 overflow rate for ...
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TH2 and TL2, respectively. A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal BOTTOM, the 16-bit value stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes ...
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Figure 12-6. Timer 2 Waveform: Auto-Reload Mode (DCEN = 1) MAX BOTTOM MIN T2EX EXF2 MAX TOP MIN 12.3.3 Dual Slope Counter When Timer 2 Auto-Reload Mode uses Count Mode 2 (T2CM (T2CM 1-0 TOP and then counts down from ...
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Figure 12-7. Timer 2 Waveform: Dual Slope Modes 12.4 Baud Rate Generator Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON 12-3). Note that the baud rates for transmit and receive can be ...
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T2EX can be used as an extra external interrupt. Also note that the Baud Rate and Frequency Generator modes may be used simultaneously. Figure 12-8. Timer 2 in Baud Rate Generator Mode OSC ÷TPS T2 PIN TRANSITION DETECTOR T2EX ...
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Figure 12-9. Timer 2 in Clock-out Mode OSC T2 PIN T2EX PIN 13. Compare/Capture Array The AT89LP3240/6440 includes a four channel Compare/Capture Array (CCA) that performs a variety of timing operations including input event capture, output compare waveform generation and ...
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Figure 13-1. Compare/Capture Array Block Diagram OSC (P1.0) T2 13.1 CCA Registers The Compare/Capture Array has five Special Function Registers: T2CCA, T2CCC, T2CCL, T2CCH and T2CCF. The T2CCF register contains the interrupt flags for each CCA channel. The CCA interrupt ...
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Table 13-1. T2CCA – Timer/Counter 2 Compare/Capture Address T2CCA Address = 0D1H Not Bit Addressable — — Bit 7 6 Symbol Function Compare/Capture Address. Selects which CCA channel is currently accessible through the T2CCH, T2CCL and T2CCC registers. Only one ...
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Table 13-4. T2CCF – Timer/Counter 2 Compare/Capture Flags T2CCF Address = 0D5H Not Bit Addressable – – Bit 7 6 Symbol Function Channel D Compare/Capture Interrupt Flag. Set by a compare/capture event on channel D. Must be cleared by software. ...
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Capture inputs are sampled every clock cycle and a new value must be held for at least 2 clock cycles to be correctly sampled by the device. The maximum ...
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Table 13-5. T2CCC – Timer/Counter 2 Compare/Capture Control T2CCC Address = 0D4H Not Bit Addressable CIENx CDIRx Bit 7 6 Symbol Function CIENx Channel X Interrupt Enable. When set, channel X’s interrupt flag, CCFx in T2CCF, will generate an interrupt ...
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Output Compare Mode The Compare/Capture Array provides a variety of compare modes suitable for event timing or waveform generation. CCA channels are configured for compare mode by setting the CCMx bit in the associated CCCx register ...
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Normal Mode The simplest waveform mode is when CP/RL2 = 0 and T2CM1-0 = 01B. In this mode the fre- quency of the output is determined by the TOP value stored in RCAP2L and RCAP2H and output edges occur ...
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Figure 13-6. Dual-Slope Waveform Example {RCAP2H,RCA2L} 13.3.2 Timer 2 Operation for Compare Mode Compare channels will work with any Timer 2 operating mode. The full 16-bit compare range may not be available in all modes. In order for a compare ...
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Asymmetrical PWM For Asymmetrical PWM, Timer 2 should be configured for Auto-Reload mode and Count Mode 1 (CP/RL2 = 0, DCEN = 0, T2CM1-0 = 01B). Asymmetrical PWM uses single slope operation as shown in TOM. In non-inverting mode, ...
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TOP point. Symmetrical PWM may be used to generate non-overlapping waveforms. The TOP value in RCAP2L and RCAP2H is double buffered such that the output frequency is only updated at the underflow. The channel ...
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Figure 13-10. Phase and Frequency Correct Symmetrical (Center-Aligned) PWM {RCAP2H,RCA2L} {CCxH,CCxL} Inverted CCx Non-Inverted Figure 13-11. Phase Correct Symmetrical (Center-Aligned) PWM {RCAP2H,RCA2L} {CCxH,CCxL} Inverted CCx Non-Inverted 13.4.3 Multi-Phasic PWM The PWM channels may be configured to provide multi-phasic alternating outputs ...
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Table 13-6. PHS 2-0 000 001 010 011 100 Figure 13-12. Multi-Phasic PWM Output Stage PHS = 001B CCA 1 EN CCB 0 EN CCC 1 EN CCD 1 EN Figure 13-13. Three-Phase Mode with Channel B Disabled CCA CCB ...
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Figure 13-14. Multi-Phasic PWM Modes CCA CCB CCC CCD CCA CCB CCC CCD CCA CCB CCC CCD PHSD CCA CCB CCC CCD PHSD CCA CCB CCC CCD 14. External Interrupts The INT0 (P3.2) and INT1 (P3.3) pins of the AT89LP3240/6440 ...
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Both INT0 and INT1 may wake up the device from the Power-down state. 15. General-purpose Interrupts The General-purpose Interrupt (GPI) function provides 8 configurable external interrupts on Port 1. Each port pin can detect high/low ...
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Table 15-1. – General-purpose Interrupt Mode Register GPMOD GPMOD = 9AH Not Bit Addressable GPMOD7 GPMOD6 Bit 7 6 GPMOD level-sensitive interrupt for P1 edge-triggered interrupt for P1.x Table 15-2. – General-purpose Interrupt Level Select ...
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Serial Interface (UART) The serial interface on the AT89LP3240/6440 implements a Universal Asynchronous Receiver/Transmitter (UART). The UART has the following features: • Full-duplex Operation • Data Bits • Framing Error Detection • Multiprocessor Communication Mode with ...
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The slaves that are not addressed set their SM2 bits and ignore the data bytes. The SM2 bit can be used to check the validity of the stop bit in ...
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Baud Rates The baud rate in Mode 0 depends on the value of the SMOD1 bit in Special Function Register PCON.7. If SMOD1 = 0 (the value on reset) and TB8 = 0, the baud rate is 1/4 of ...
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Table 16-2. Baud Rate Mode 0: 1 MHz Mode 2: 750K 62.5K 38.4K 19.2K 9.6K 4.8K 2.4K 1.2K 137.5 16.2.2 Using Timer 2 to Generate Baud Rates Timer 2 is selected as the baud rate generator by setting TCLK and/or ...
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More About Mode 0 In Mode 0, the UART is configured as a two wire half-duplex synchronous serial interface. Serial data enters and exits through RXD. TXD outputs the shift clock. Eight data bits are transmit- ted/received, with the ...
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Figure 16-1. Serial Port Mode 0 TIMER 1 OVERFLOW f osc 1 0 TB8 ÷2 ÷ SMOD1 WRITE TO SBUF SEND SHIFT RXD (DATA OUT) TXD (SHIFT CLOCK) TI WRITE TO SCON (CLEAR RI) RI RECEIVE SHIFT RXD ...
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Figure 16-2. Mode 0 Waveforms SMOD1 = 0 TXD SM2 = 0 RXD (TX) RXD (RX) SMOD1 = 1 TXD SM2 = 0 RXD (TX) RXD (RX) SMOD1 = 0 TXD SM2 = 1 RXD (TX) RXD (RX) SMOD1 = ...
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More About Mode 1 Ten bits are transmitted (through TXD), or received (through RXD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in SCON. In ...
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Figure 16-4. Serial Port Mode 1 TIMER 1 TIMER 2 OVERFLOW OVERFLOW WRITE ÷2 TO SBUF “0” “1” SMOD1 “0” “1” TCLK “0” “1” INTERRUPT RCLK SAMPLE 1-TO-0 TRANSITION DETECTOR RXD TX CLOCK WRITE TO SBUF SEND DATA SHIFT D0 ...
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More About Modes 2 and 3 Eleven bits are transmitted (through TXD), or received (through RXD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the 9th ...
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Figure 16-5. Serial Port Mode 2 CPU CLOCK SMOD1 1 SMOD1 0 3706C–MICRO–2/11 AT89LP3240/6440 INTERNAL BUS INTERNAL BUS 95 ...
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Figure 16-6. Serial Port Mode 3 TIMER 1 TIMER 2 OVERFLOW OVERFLOW WRITE TO ÷2 SBUF “0” “1” SMOD1 “0” “1” TCLK “0” “1” INTERRUPT RCLK SAMPLE 1-TO-0 TRANSITION DETECTOR RXD TX CLOCK WRITE TO SBUF SEND DATA SHIFT D0 ...
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Framing Error Detection In addition to all of its usual modes, the UART can perform framing error detection by looking for missing stop bits, and automatic address recognition. When used for framing error detect, the UART looks for missing ...
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In a more complex system, the following could be used to select slaves 1 and 2 while excluding slave 0: Slave 0 Slave 1 Slave 2 In the above example, the differentiation among the 3 slaves is in the lower ...
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Figure 17-1. SPI Block Diagram T1 OVF The interconnection between master and slave CPUs with SPI is shown in pins in the interface are Master-In/Slave-Out (MISO), Master-Out/Slave-In (MOSI), Shift Clock (SCK), and Slave Select (SS). The SCK pin is the ...
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Figure 17-2. SPI Master-Slave Interconnection When the SPI is configured as a Master (MSTR in SPCR is set), the operation of the SS pin depends on the setting of the Slave Select Ignore bit, SSIG. If SSIG = 1, the ...
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ENH bit in SPSR is set. For multi-byte transfers, TXE may be used to remove any dead time between byte transmissions. The SPI master can operate in two modes: multi-master mode and single-master mode. By default, multi-master ...
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Table 17-1. Pin SCK MOSI MISO Notes: Table 17-2. SPCR – SPI Control Register SPCR Address = E9H Not Bit Addressable TSCK SPE Bit 7 6 Symbol Function SCK Clock Mode. When TSCK = 0, the SCK baud rate ...
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Symbol Function SPI clock rate select. These two bits control the SCK rate of the device configured as master. SPR1 and SPR0 have no effect on the slave. The relationship between SCK and the oscillator frequency, F SPR1 SPR0 SCK ...
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Slave Select Ignore. If SSIG = 0, the SPI will only operate in slave mode if SS (P1.4) is pulled low. When SSIG = 1, the SPI ignores SS in slave mode and is active whenever SPE (SPCR.6) is set. ...
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Two-Wire Serial Interface The Two-Wire Interface (TWI bi-directional 2-wire serial communication standard designed primarily for simple but efficient integrated circuit (IC) control. The system is comprised of two lines, SCL (Serial Clock) and SDA (Serial ...
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Data Transfer and Frame Format 18.1.1 Transferring Bits Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level of the data line must be stable when the clock line is ...
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SDA line should be left high in the ACK clock cycle. The Master can then transmit a STOP condition REPEATED START condition to initiate a new transmission. An address packet consisting of a slave address ...
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Combining Address and Data Packets Into a Transmission A transmission basically consists of a START condition, a SLA+R/W, one or more data packets and a STOP condition. An empty message, consisting of a START followed by a STOP condi- ...
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Figure 18-7. SCL Synchronization between Multiple Masters SCL from Master A SCL from Master B SCL bus Arbitration is carried out by all masters continuously monitoring the SDA line after outputting data. If the value read from the SDA line ...
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It is the user software’s responsibility to ensure that these illegal arbitration conditions never occur. This implies that in multi-master systems, all data transfers must use the same composi- tion of SLA+R/W and data packets. In other words: All transmissions ...
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TWI bus clock period. The SCL frequency is generated according to the following equation: 18.3.3 Bus Interface Unit This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller and Arbitration detection hardware. The TWDR contains the ...
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Register Overview Table 18-1. TWCR – Two-Wire Control Register TWCR Address = AAH Not Bit Addressable – TWEN Bit 7 6 Symbol Function TWEN Two-wire Serial Interface Enable. Set to enable the TWI. Clear to disable the TWI. STA ...
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Table 18-4. TWDR – Two-Wire Data Register TWDR Address = ADH Not Bit Addressable TWD7 TWD6 Bit 7 6 Symbol Function Two-wire Interface Data. Writes to TWDR queue the next address or data byte for transmission. Reads from TWDR TWD ...
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Figure 18-10. Interfacing the Application to the TWI in a Typical Transmission 1. Application writes 3. Check TWSR to see if START was to TWCR to initiate sent. Application loads SLA+W into transmission of TWDR, and loads appropriate control START ...
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TWIF bit in TWCR is set. Immediately after the application has cleared TWIF, the TWI will initiate transmission of the data packet. 6. When the data packet has been transmitted, the TWIF flag in TWCR is set, ...
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SLA: Slave Address In Figure 18-11 bers in the circles show the status code held in TWSR. At these points, actions must be taken by the application to continue or complete the TWI transfer. The TWI transfer is suspended until ...
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Table 18-6. Status Codes for Master Transmitter Mode Status Status of the Two-wire Code Serial Bus and Two-wire (TWSR) Serial Interface Hardware A START condition has 0x08 been transmitted A repeated START 10h condition has been transmitted SLA+W has ...
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Figure 18-11. Format and States in Master Transmitter Mode Successfull S SLA transmission to a slave receiver 08h Next transfer started with a repeated start condition Not acknowledge received after the slave address Not acknowledge received after a data byte ...
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TWEN must be written to one to enable the Two-wire Serial Interface, STA must be written to one to transmit a START condition and TWIF must be cleared. The TWI will then test the Two- wire Serial Bus and generate ...
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Figure 18-12. Format and States in Master Receiver Mode Successfull S SLA reception from a slave receiver 08h Next transfer started with a repeated start condition Not acknowledge received after the slave address Arbitration lost in slave address or data ...
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TWEN must be written to one to enable the TWI. The AA bit must be written to one to enable the acknowledgment of the device’s own slave address or the general call address. STA and STO must be written to ...
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Table 18-8. Status Codes for Slave Receiver Mode Previously addressed with own SLA+W; data has been 88h received; NOT ACK has been returned Previously addressed with general call; data has been 90h received; ACK has been returned Previously addressed with ...
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Slave Transmitter Mode In the Slave Transmitter mode, a number of data bytes are transmitted to a master receiver. To initiate the Slave Transmitter mode, upper 7 bits of TWAR must be initialized with the address to which the ...
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Table 18-9. Status Codes for Slave Transmitter Mode Status Status of the Two-wire Code Serial Bus and Two-wire (TWSR) Serial Interface Hardware Own SLA+R has been A8h received; ACK has been returned Arbitration lost in SLA+R/W as master; own ...
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Miscellaneous States There are two status codes that do not correspond to a defined TWI state, see Status F8h indicates that no relevant information is available because the TWIF flag is not set. This occurs between other states, and ...
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Figure 18-15. Combining Several TWI Modes to Access a Serial EEPROM START 19. Dual Analog Comparators The AT89LP3240/6440 provides two analog comparators. The analog comparators have the fol- lowing features: • Internal 3-level Voltage Reference (1.2V, 1.3V, ...
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CONA (ACSRA.5) or CONB (ACSRB.5) bits to connect the comparator inputs before using a comparator. When a comparator is first enabled, the comparator output and inter- rupt flag are not guaranteed to be stable for 10 µs. ...
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Figure 19-2. Equivalent Analog Input Model 19.2 Internal Reference Voltage The negative input terminal of each comparator may be connected to an internal voltage refer- ence by changing the RFB set to 1.3 V ±5%. The voltage reference also provides ...
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Figure 19-4. Dual Comparator Configuration Examples a. dual independent comparators with external references + AIN0 A - AIN1 CSA = 00 RFA = 00 b. 3-channel comparator with external reference AIN0 AIN2 AIN1 AIN3 CSA = 00/10/11 RFA = 00 ...
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Table 19-1. – Analog Comparator A Control & Status Register ACSRA ACSRA = 97H Not Bit Addressable CSA1 CSA0 Bit 7 6 Symbol Function CSA [1-0] Comparator A Positive Input Channel Select CSA1 CSA0 A+ Channel 0 0 AIN0 (P2.4) ...
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Table 19-2. – Analog Comparator B Control & Status Register ACSRB ACSRB = 9FH Not Bit Addressable CSB1 CSB0 Bit 7 6 Symbol Function CSB [1-0] Comparator B Positive Input Channel Select CSB1 CSB0 ...
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Table 19-3. – Analog Comparator Reference Control Register AREF AREF = AFH Not Bit Addressable CBC1 CBC0 Bit 7 6 Symbol Function CSC [1-0] Comparator B Clock Select CBC1 CBC0 Clock Source 0 0 System Clock 0 0 Timer 0 ...
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Digital-to-Analog/Analog-to-Digital Converter The AT89LP3240/6440 includes a 10-bit Data Converter (DADC) with the following features: • Digital-to-Analog (DAC) or Analog-to-Digital (ADC) Mode • 10-bit Resolution • 6.5 µs Conversion Time • 8 Multiplexed Single-ended Channels or 4 Differential Channels • ...
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Table 20-1. Right Adjust 0 0100h 01FFh FF00h FE01h Figure 20-1. DADC Block Diagram 8-BIT DATA BUS VDD R R GND INTERNAL 1.0V REFERENCE ADC7 ADC6 ADC5 ADC4 POS. INPUT MUX ADC3 ADC2 ADC1 ADC0 NEG. INPUT MUX AVDD/2 AT89LP3240/6440 ...
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ADC Operation The ADC converts an analog input voltage to a 10-bit signed digital value through successive approximation. When DIFF (DADI.3) is zero, the ADC operates in single-ended mode and the input voltage is the difference between the voltage ...
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Figure 20-3. Equivalent Analog Input Model 20.2 DAC Operation The DAC converts a 10-bit signed digital value to an analog output current through successive approximation. The DAC always operates in differential mode, outputting a differential current between its positive (P2.2) ...
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Figure 20-5. Equivalent Analog Output Model 20.3 Clock Selection The DADC requires a clock of 2 MHz or less to achieve full resolution. By default the DADC will use an internal 2 MHz clock generated from the 8 MHz internal ...
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Note that the timer overflow rate must be slower than the conversion time. 20.5 Noise Considerations Digital circuitry inside and outside the device generates EMI which might affect the accuracy ...
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Table 20-2. – DADC Control Register DADC DADC = D9H Not Bit Addressable ADIF GO/BSY Bit 7 6 Symbol Function ADIF ADC Interrupt Flag. Set by hardware when a conversion completes. Cleared by hardware when calling the interrupt service routine. ...
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Table 20-5. – DADC Input Control Register DADI DADI = DAH Not Bit Addressable ACON IREF Bit 7 6 Symbol Function ACON Analog Input Connect. When cleared, the analog inputs are disconnected from the ADC. When set, the analog inputs ...
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Programmable Watchdog Timer The programmable Watchdog Timer (WDT) protects the system from incorrect execution by trig- gering a system reset when it times out after the software has failed to feed the timer prior to the timer overflow. By ...
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Software Reset A Software Reset of the AT89LP3240/6440 is accomplished by writing the software reset sequence 5AH/A5H to the WDTRST SFR. The WDT does not need to be enabled to generate the software reset. A normal software reset will ...
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Instruction Set Summary The AT89LP3240/6440 is fully binary compatible with the 8051 instruction set. The difference between the AT89LP3240/6440 and the standard 8051 is the number of cycles required to exe- cute an instruction. Instructions in the AT89LP3240/6440 may ...
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Table 22-1. INC /DPTR MUL AB DIV MAC AB (1) CLR M (1) ASR M (1) LSL M Bit Operations CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C, bit ANL C, ...
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Table 22-1. XRL A, direct XRL A, @Ri XRL A, #data XRL direct, A XRL direct, #data RL A RLC RRC A SWAP A Data Transfer MOV A, Rn MOV A, direct MOV A, @Ri MOV A, ...
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Table 22-1. POP direct XCH A, Rn XCH A, direct XCH A, @Ri XCHD A, @Ri Branching JC rel JNC rel JB bit, rel JNB bit, rel JBC bit, rel JZ rel JNZ rel SJMP rel ACALL addr11 LCALL addr16 ...
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Instruction Set Extensions The following instructions are extensions to the standard 8051 instruction set that provide enhanced capabilities not found in standard 8051 devices. All extended instructions start with an A5H escape code. For this reason random A5H reserved ...
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CJNE rel i Function: Compare and Jump if Not Equal Description: CJNE compares the magnitudes of the Accumulator and indirect RAM location and branches if their values are not equal. The branch destination is computed by ...
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INC /DPTR Function: Increment Alternate Data Pointer Description: INC /DPTR increments the unselected 16-bit data pointer 16-bit increment (modulo 2 and an overflow of the low-order byte of the data pointer from 0FFH to 00H increments ...
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LSL M Function: Shift MAC Accumulator Left Logically Description: The forty bits in the M register are shifted one bit to the left. Bit 0 is cleared. No flags are affected. Example: The M register holds the value 0C5B1A29384H. ...
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MAC AB Function: Multiply and Accumulate Description: MAC AB multiplies the signed 16-bit integers in the register pairs {AX, A} and {BX, B} and adds the 32-bit product to the 40-bit M register. The low-order bytes of the 16-bit ...
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MOVX A, @/DPTR Function: Move External using Alternate Data Pointer Description: The MOVX instruction transfesr data from external data memory to the Accumulator. The unselected Data Pointer generates a 16-bit address which targets EDATA, FDATA or XDATA. Example: DPS ...
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Register Index Table 23-1. Name ACC ACSRA ACSRB AREF AUXR CLKREG DADC DADH DADI DADL DPCF (AUXR1) DPH0 DPH1 DPL0 DPL1 DSPR FIRD GPIEN GPIF GPLS GPMOD IE IE2 IP IP2 IPH IPH2 MACH MACL MEMCON ...
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Table 23-1. P1 P1M0 P1M1 P2 P2M0 P2M1 P3 P3M0 P3M1 P4 P4M0 P4M1 PAGE PCON PSW RCAP2H RCAP2L RH0 RH1 RL0 RL1 SADDR SADEN SBUF SCON SP SPCR SPDR SPSR SPX T2CCA T2CCC T2CCF T2CCH T2CCL T2CON T2MOD TCON ...
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Table 23-1. TH0 TH1 TH2 TL0 TL1 TL2 TMOD TWAR TWBR TWCR TWDR TWSR WDTCON WDTRST 24. On-Chip Debug System The AT89LP3240/6440 On-Chip Debug (OCD) System uses a two-wire serial interface to con- trol program flow; read, modify, and write ...
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P4.2/RST cannot be connected directly to V must be removed. • All external reset sources must be removed. • If P4.3 needs to be debugged in systems using the crystal oscillator, the external clock option should be selected. The ...
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When using the Internal RC Oscillator during debug, DDA is located on the XTAL1/P4.0 pin. The P4.0 I/O function cannot be emulated in this mode. • When using the External Clock during debug, DDA is located on the XTAL2/P4.1 ...
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Figure 25-1. In-System Programming Device Connections The Parallel interface is a special mode of the serial interface, i.e. the serial interface is used to enable the parallel interface. After enabling the interface serially over P1.7/SCK and P1.5/MOSI, P1.5 is reconfigured ...
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... Table 25-1. Memory CODE User Signature Atmel Signature 3706C–MICRO–2/11 Table 25-1 and AT89LP3240/6440 Memory Organization Capacity 32KB (AT89LP3240) 64KB (AT89LP6440) DATA 8192 bytes 256 bytes 128 bytes AT89LP3240/6440 Figure 25-3. The memory is divided into pages of 128 Page Size # Pages 128 bytes 256 ...
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... Figure 25-3. AT89LP6440 Memory Organization 25.3 Command Format Programming commands consist of an opcode byte, two address bytes, and zero or more data bytes. In addition, all command packets must start with a two-byte preamble of AAH and 55H. The preamble increases the noise immunity of the programming interface by making it more dif- ficult to issue unintentional commands ...
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For a summary of available commands, see Figure 25-4. Command Sequence Flow Chart Figure 25-5. ISP Command Packet (Serial) SS SCK MOSI Preamble 1 MISO X Figure 25-6. ISP Command Packet (Parallel) SS SCK OE P0 AAh OE P0 AAh ...
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... Each byte address selects one fuse or lock bit. Data bytes must be 00h or FFh. 5. See Table 25-5 on page 164 6. See Table 25-4 on page 163 7. Atmel Signature Bytes: Address: 0000H AT89LP3240: 1EH AT89LP6440: 1EH 8. Symbol Key: a: Page Address Bit s: Half Page Select Bit b: Byte Address Bit x: Don’ ...
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Status Register The current state of the memory may be accessed by reading the status register. The status reg- ister is shown in Table 25-3. Register Status – – Bit 7 6 Symbol Function Load flag. Cleared low by ...
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User Configuration Fuses The AT89LP3240/6440 includes 11 user fuses for configuration of the device. Each fuse is accessed at a separate address in the User Fuse Row as listed in by programming 00h to their locations. Programming FFh to ...
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User Signature and Analog Configuration The User Signature Array contains 256 bytes of non-volatile memory in two 128-byte pages. The first page of the User Signature Array (0000H–007FH) is available for serial numbers, firmware revision information, date codes or ...
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Figure 25-7. Serial Programming Power-up Sequence MISO MOSI 25.9.2 Power-down Sequence Execute this sequence to power-down the device after programming. 1. Drive SCK low. 2. Wait at least t 3. Tristate MOSI. 4. Wait at least t 5. Wait no ...
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Figure 25-9. In-System Programming (ISP) Start Sequence 25.9.4 ISP Exit Sequence Execute this sequence to exit ISP mode and resume CPU execution mode. 1. Drive SCK low. 1. Wait at least t 2. Tristate MOSI. 3. Wait at least t ...
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CPHA = 0) where bits are sampled on the rising edge of SCK and output on the falling edge of SCK. For more detailed timing information see Figure 25-11. ISP Byte Sequence Figure 25-12. Serial Programming Interface Timing SS SCK ...
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Timing Parameters The timing parameters for Figure 25-13 Table 25-7. Symbol t CLCL t PWRUP t t PWRDN SHSL t SLSH ...
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Electrical Characteristics 26.1 Absolute Maximum Ratings* Operating Temperature ................................... -40°C to +85°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground......-0.7V to +3.6V Maximum Operating Voltage ............................................ 3.6V DC Current per I/O Pin .................................................. ...
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Safe Operating Conditions 26.3.1 Speed Figure 26-1 age. The device is only gauranteed to operate correctly within this area. Note that the on-chip Brown-out Detector (BOD) has a minimum threshold of 1.8V. Systems that rely on this BOD to ...
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Supply Current (Internal Oscillator) Figure 26-3. Active Supply Current vs. V Figure 26-4. Idle Supply Current vs. V AT89LP3240/6440 172 DD Active Supply Current vs. Vcc 8MHz Internal Oscillator 6.5 6.0 5.5 5.0 4.5 4.0 3.5 2.4 2.7 3.0 ...
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Supply Current (External Clock) Figure 26-5. Active Supply Current vs. Frequency Figure 26-6. Idle Supply Current vs. Frequency 3706C–MICRO–2/11 Active Supply Current vs. Frequency External Clock Source ...
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Quasi-Bidirectional Input Figure 26-7. Quasi-bidirectional Input Transition Current at 3.3V 26.4.4 Quasi-Bidirectional Output Figure 26-8. Quasi-Bidirectional Output I-V Source Characteristic at 3V AT89LP3240/6440 174 0.0 0.4 0.8 1.2 1.6 0 -20 -40 -60 -80 -100 -120 V (V) IL ...
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Push-Pull Output Figure 26-9. Push-Pull Output I-V Source Characteristic at 3V Figure 26-10. Push-Pull Output I-V Sink Characteristic at 3V Note: 26.5 Clock Characteristics Figure 26-11. External Clock Drive Waveform 3706C–MICRO–2/11 2.4 2.5 2 ...
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The values shown in these tables are valid for T Table 26-1. External Clock Parameters Symbol Parameter (1) 1/t Oscillator Frequency CLCL t Clock Period CLCL t External Clock High Time CHCX t External Clock Low Time CLCX t External ...
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Figure 26-13. Typical Crystal Oscillator Swing with Quartz Crystal and C1=C2, T 4.0 3.5 3.0 2.5 2.0 4 Note: 1. Replacing capacitor C1 with a resistor MΩ results in similar swing levels on XTAL1. Figure 26-14. Typical ...
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Reset Characteristics The values shown in this table are valid for T Table 26-3. Reset Characteristics Symbol Parameter R Reset Pull-up Resistor RST V Power-On Reset Threshold POR V Brown-Out Detector Threshold BOD V Brown-Out Detector Hysteresis BH t ...
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Parameter t applies only when ALES = 1. LHLL 4. The strobe pulse width may be lengthened additional t 5. Parameter t applies only when ALES = 0, or when two MOVX instructions occur ...
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Table 26-5. SPI Master Characteristics Symbol Parameter t Serial Input Setup Time SIS t Serial Input Hold Time SIH t Serial Output Hold Time SOH t Serial Output Valid Time SOV Table 26-6. SPI Slave Characteristics Symbol Parameter t Oscillator ...
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Figure 26-18. SPI Slave Timing (CPHA = 0) SS SCK (CPOL = 0) SCK (CPOL= 1) MISO MOSI Figure 26-19. SPI Master Timing (CPHA = 1) SS SCK (CPOL = 0) SCK (CPOL = 1) MISO MOSI Figure 26-20. SPI ...
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Two-wire Serial Interface Characteristics Table 26-7 describes the requirements for devices connected to the Two-wire Serial Bus. The AT89LP3240/6440 Two-wire Serial Interface meets or exceeds these requirements under the noted conditions. The values shown in this table are valid ...
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C = capacitance of one bus line in pF CPU clock frequency CK Figure 26-21. Two-wire Serial Bus Timing SCL t t SU;STA HD;STA SDA 26.10 Serial Port Timing: Shift Register Mode The values in ...
Page 184
Dual Analog Comparator Characteristics The values shown in this table are valid for T Table 26-8. Dual Analog Comparator Characteristics Symbol Parameter V Common Mode Input Voltage CM V Input Offset Voltage OS V Analog Reference Voltage AREF V ...
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DADC Characteristics The values shown in these tables are valid for T Table 26-9. ADC Characteristics Symbol Parameter Resolution Absolute Accuracy (including INL, DNL, quantization error, gain and offset error) Integral Non-Linearity (INL) DIfferential Non-Linearity (DNL) Gain Error Offset ...
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Test Conditions 26.13.1 AC Testing Input/Output Waveform Figure 26-24. AC Testing Input/Output Waveform Note: 26.13.2 Float Waveform Figure 26-25. Float Waveform Note: 26.13.3 I Test Condition: Active Mode CC Figure 26-26. Connection Diagram for I For active supply current ...
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I Test Condition: Idle Mode CC Figure 26-27. Connection Diagram for I 26.13.5 Clock Signal Waveform for I Figure 26-28. Clock Signal Waveform for I 26.13.6 I Test Condition: Power-down Mode CC Figure 26-29. Connection Diagram for I 3706C–MICRO–2/11 ...
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... Body, Plastic Very Thin Quad Flat No Lead Package (VQFN/MLF) AT89LP3240/6440 188 Ordering Code AT89LP3240-20AU AT89LP3240-20PU AT89LP3240-20JU AT89LP3240-20MU AT89LP6440-20AU AT89LP6440-20PU AT89LP6440-20JU AT89LP6440-20MU Package Types Package Operation Range 44A 40P6 44J 44M1 Industrial (-40° 85° C) 44A 40P6 44J 44M1 3706C– ...
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Packaging Information 28.1 44A – TQFP PIN 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per ...
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PDIP A SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed ...
Page 191
PLCC 1.14(0.045) X 45˚ 0.51(0.020)MAX 45˚ MAX (3X) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per ...
Page 192
VQFN/MLF D Marked Pin TOP VIEW BOTTOM VIEW Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-3. Package Drawing Contact: packagedrawings@atmel.com AT89LP3240/6440 192 E Pin #1 Corner Pin #1 ...
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Revision History Revision No. Revision A – September 2009 Revision B– September 2010 Revision C– February 2011 3706C–MICRO–2/11 AT89LP3240/6440 History • Initial Release • Removed Preliminary status • Updated “DC Characteristics” on page 170 • Updated “Typical Characteristics” on ...
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AT89LP3240/6440 194 3706C–MICRO–2/11 ...
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Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 2 Overview ................................................................................................... 6 3 Memory Organization ............................................................................ 11 4 Special Function Registers ................................................................... 22 5 Enhanced CPU ....................................................................................... 23 6 System Clock ......................................................................................... 31 7 Reset ....................................................................................................... 33 ...
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Table of Contents (Continued) 8 Power Saving Modes ............................................................................. 36 9 Interrupts ................................................................................................ 39 10 I/O Ports .................................................................................................. 45 11 Enhanced Timer 0 and Timer 1 with PWM ........................................... 51 12 Enhanced Timer 2 .................................................................................. 60 13 Compare/Capture Array ........................................................................ ...
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Table of Contents (Continued) 16 Serial Interface (UART) .......................................................................... 85 17 Enhanced Serial Peripheral Interface .................................................. 98 18 Two-Wire Serial Interface .................................................................... 105 19 Dual Analog Comparators ................................................................... 126 20 Digital-to-Analog/Analog-to-Digital Converter .................................. 133 21 Programmable Watchdog Timer ......................................................... 141 ...
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Table of Contents (Continued) 22 Instruction Set Summary .................................................................... 143 23 Register Index ...................................................................................... 153 24 On-Chip Debug System ....................................................................... 155 25 Programming the Flash Memory ........................................................ 157 26 Electrical Characteristics .................................................................... 170 27 Ordering Information ........................................................................... 188 AT89LP3240/6440 iv ...
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Table of Contents (Continued) 28 Packaging Information ........................................................................ 189 29 Revision History ................................................................................... 193 Table of Contents....................................................................................... i 3706C–MICRO–2/11 28.1 44A – TQFP ...................................................................................................189 28.2 40P6 – PDIP ..................................................................................................190 28.3 44J – PLCC ...................................................................................................191 28.4 44M1 – VQFN/MLF .......................................................................................192 AT89LP3240/6440 ...
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