AT89LP6440 Atmel Corporation, AT89LP6440 Datasheet - Page 82

no-image

AT89LP6440

Manufacturer Part Number
AT89LP6440
Description
Manufacturer
Atmel Corporation
Datasheet

Specifications of AT89LP6440

Flash (kbytes)
64 Kbytes
Max. Operating Frequency
20 MHz
Cpu
8051-1C
Max I/o Pins
38
Spi
1
Twi (i2c)
1
Uart
1
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
153.8
Sram (kbytes)
4.25
Eeprom (bytes)
8192
Self Program Memory
IAP
Operating Voltage (vcc)
2.4 to 3.6
Timers
3
Isp
SPI/OCD
Watchdog
Yes

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT89LP6440-20AU
Manufacturer:
Cirrus
Quantity:
89
Part Number:
AT89LP6440-20AU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT89LP6440-20JU
Manufacturer:
Atmel
Quantity:
103
Part Number:
AT89LP6440-20JU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT89LP6440-20MU
Manufacturer:
Atmel
Quantity:
987
Figure 13-14. Multi-Phasic PWM Modes
14. External Interrupts
82
AT89LP3240/6440
PHSD
PHSD
CCA
CCB
CCC
CCD
CCA
CCB
CCC
CCD
CCA
CCB
CCC
CCD
CCA
CCB
CCC
CCD
CCA
CCB
CCC
CCD
The INT0 (P3.2) and INT1 (P3.3) pins of the AT89LP3240/6440 may be used as external inter-
rupt sources. The external interrupts can be programmed to be level-activated or transition-
activated by setting or clearing bit IT1 or IT0 in Register TCON. If ITx = 0, external interrupt x is
triggered by a detected low at the INTx pin. If ITx = 1, external interrupt x is edge-triggered. In
this mode if successive samples of the INTx pin show a high in one cycle and a low in the next
cycle, interrupt request flag IEx in TCON is set. Flag bit IEx then requests the interrupt. Since the
external interrupt pins are sampled once each clock cycle, an input high or low should hold for at
least 2 oscillator periods to ensure sampling. If the external interrupt is transition-activated, the
external source has to hold the request pin high for at least two clock cycles, and then hold it low
for at least two clock cycles to ensure that the transition is seen so that interrupt request flag IEx
will be set. IEx will be automatically cleared by the CPU when the service routine is called if gen-
erated in edge-triggered mode. If the external interrupt is level-activated, the external source has
to hold the request active until the requested interrupt is actually generated. Then the external
source must deactivate the request before the interrupt service routine is completed, or else
PHS = 000B
PHS = 001B
PHS = 010B
PHS = 011B
PHS = 100B
3706C–MICRO–2/11

Related parts for AT89LP6440