AT89LP6440 Atmel Corporation, AT89LP6440 Datasheet - Page 113

• Manufacturer Part Number: AT89LP6440
• Manufacturer: Atmel Corporation

Specifications of AT89LP6440

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 38
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 4.25
• Eeprom (bytes): 8192
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 3.6
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

Table 18-4.
Table 18-5.
18.5
3706C–MICRO–2/11
TWDR Address = ADH
Not Bit Addressable
Symbol
TWD
TWBR Address = AEH
Not Bit Addressable
Symbol
TWB
Bit
Bit
7-0
7-0
Using the TWI
TWD7
TWB7
Function
Two-wire Interface Data. Writes to TWDR queue the next address or data byte for transmission. Reads from TWDR
return the last address or data byte present on the bus. Writes/reads to/from TWDR must occur only while TWIF is set.
Writes to TWDR while TWIF = 0 are ignored. Reads from TWDR while TWIF = 0 may return random data.
Function
Two-wire Interface Serial Bit Rate. TWBR is an 8-bit down counter that selects the division factor (÷1–256) for the bit rate
generator. The bit rate generator is a frequency divider which generates the SCL clock frequency from the system clock
in Master mode.
7
7
TWDR – Two-Wire Data Register
TWBR – Two-Wire Bit Rate Register
TWD6
TWB6
The AT89LP TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events,
like reception of a byte or transmission of a START condition. Because the TWI is interrupt-
based, the application software is free to carry on other operations during a TWI byte transfer.
Note that the TWI Interrupt Enable (TWE) bit in IE2 together with the Global Interrupt Enable bit
in EA allow the application to decide whether or not assertion of the TWIF flag should generate
an interrupt request. If the TWE bit is cleared, the application must poll the TWIF flag in order to
detect actions on the TWI bus.
When the TWIF flag is asserted, the TWI has finished an operation and awaits application
response. In this case, the TWI Status Register (TWSR) contains a value indicating the current
state of the TWI bus. The application software can then decide how the TWI should behave in
the next TWI bus cycle by manipulating the TWCR and TWDR registers.
Figure 18-10
this example, a Master wishes to transmit a single data byte to a Slave. This description is quite
abstract, a more detailed explanation follows later in this section. A simple code example imple-
menting the desired behavior is also presented.
6
6
TWD5
TWB5
is a simple example of how the application can interface to the TWI hardware. In
5
5
TWD4
TWB4
4
4
TWD3
TWB3
3
3
TWD2
TWB2
2
2
AT89LP3240/6440
Reset Value = 1111 1111B
Reset Value = 0000 0000B
TWD1
TWB1
1
1
TWD0
TWB0
0
0
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