AT89LP828 Atmel Corporation, AT89LP828 Datasheet
AT89LP828
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AT89LP828 Summary of contents
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... Push-pull CMOS Output • Open-drain • Operating Conditions – 2.4V to 5.5V V Voltage Range CC – -40°C to 85°C Temperature Range – MHz @ 2.4–5.5V – MHz @ 4.0–5.5V ® 51 Products 8-bit Microcontroller with 4K/8K Bytes In-System Programmable Flash AT89LP428 AT89LP828 3654A–MICRO–8/09 ...
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Pin Configurations 1.1 28P3 – 28-lead PDIP AIN1/P2 P2.6/AIN2 AIN0/P2 P2.7/AIN3 RXD/P3 P1.7/SCK TXD/P3 P1.6/MISO XTAL2/P4 P1.5/MOSI XTAL1/P4 P1.4/SS GND 7 22 P1.3 INT0/P3 VCC ...
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Pin Description Table 1-1. AT89LP428/828 Pin Description Pin Number TQFP /MLF PLCC PDIP Symbol P4 P4 N/A P4 GND 5 9 N/A P4 P3.2 7 ...
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Table 1-1. AT89LP428/828 Pin Description (Continued) Pin Number TQFP /MLF PLCC PDIP Symbol P1 P1 N/A P4 VCC 21 25 N ...
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Overview The AT89LP428/828 is a low-power, high-performance CMOS 8-bit microcontroller with 4K/8K bytes of In-System Programmable Flash program memory and 512/1024 bytes of Flash data memory. The device is manufactured using Atmel ogy and is compatible with the industry-standard ...
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Block Diagram Figure 2-1. AT89LP428/828 Block Diagram 4K/8K Bytes Flash Code General-purpose Interrupt Port 1 Configurable I/O Port 2 Configurable I/O Port 3 Configurable I/O Port 4 Configurable I/O POR BOD Crystal or Configurable Resonator Oscillator Internal RC Oscillator ...
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Comparison to Standard 8051 The AT89LP428/828 is part of a family of devices with enhanced features that are fully binary compatible with the MCS-51 instruction set. In addition, most SFR addresses, bit assignments, and pin alternate functions are identical ...
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... RAM and 128 bytes of Special Function Register I/O space. The AT89LP428/828 does not support external data memory or external program memory; however, portions of the external data memory space are implemented on chip as Extra RAM and nonvolatile Flash data memory. The memory address spaces of the AT89LP428 and AT89LP828 are listed in Tables 3-1 and Table 3-1. ...
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... Data stored in the signature array is not secure. Security bits will disable writes to the array; however, reads by an external device programmer are always allowed. 3654A–MICRO–8/09 AT89LP828 Memory Address Spaces Description Directly addressable internal RAM Indirectly addressable internal RAM and stack space ...
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In order to read from the signature arrays, the SIGEN bit (DPCF.3) must be set. While SIGEN is one, MOVC A,@A+DPTR will access the signature arrays. The User Signature Array is mapped from addresses 0080H to 00FFH and the Atmel ...
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... EDATA Page Register PAGE – – – Function Selects which 256-byte page of EDATA is currently accessible by MOVX @Ri instructions. AT89LP428/828 Figure 3-3. These memory spaces may AT89LP828 05FF Flash Data (FDATA) 0200 01FF Extra RAM (EDATA) 0000 Reset Value = XXXX XXX0B – – – ...
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... When IAP = 0 and DMEN = 1, the Flash data memory is mapped into the FDATA space, directly above the EDATA space near the bottom of the external memory address space. (Addresses 0200H–03FFH on AT89LP428 and 0200H–05FFH on AT89LP828. See on page ory. FDATA is not accessible while DMEN = 0. FDATA can be accessed only by 16-bit (MOVX @DPTR) addresses ...
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Figure 3-4. Figure 3-5. The auto-erase bit AERS (MEMCON.6) can be set to one to perform a page erase automatically at the beginning of any write sequence. The page erase will erase the entire page and then the bytes in ...
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Table 3-4. – Memory Control Register MEMCON MEMCON = 96H Not Bit Addressable IAP AERS Bit 7 6 Symbol Function IAP In-Application Programming Enable. When IAP = 1 and the IAP Fuse is enabled, programming of the CODE/SIG space is ...
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Special Function Registers A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. ...
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Enhanced CPU The AT89LP428/828 uses an enhanced 8051 CPU that runs times the speed of stan- dard 8051 devices ( times the speed of X2 8051 devices). The increase in performance is ...
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Figure 5-3. Fetch Immediate Operand 5.1 Enhanced Dual Data Pointers The AT89LP428/828 provides two 16-bit data pointers: DPTR0 formed by the register pair DPOL and DPOH (82H an 83H), and DPTR1 formed by the register pair DP1L and DP1H (84H ...
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For assemblers that do not support this notation, the 0A5H prefix must be declared in-line: EX: A summary of data pointer instructions with fast context switching is listed in Table 5-1. JMP @A+DPTR MOV DPTR, #data16 MOV/DPTR, #data16 INC DPTR ...
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Table 5-3. DPD1 Table 5-4. DPCF = A2H Not Bit Addressable Bit Symbol DPU1 DPU0 DPD1 DPD0 SIGEN DPS 3654A–MICRO–8/09 DPTR Auto-update Operation for MOVX and MOVC (DPU1 = 1 & DPU0 = 1) DPS = ...
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... All the instructions related to jumping or branching should be restricted such that the destination address falls within the physical program memory space of the device, which is 0000H–0FFFH for the AT89LP428 and 0000H–1FFFH for the AT89LP828. This should be the responsibility of the software programmer. For example, LJMP 07E0H would be a valid instruc- tion, whereas LJMP 9000H would not ...
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Crystal Oscillator When enabled, the internal inverting oscillator amplifier is connected between XTAL1 and XTAL2 for connection to an external quartz crystal or ceramic resonator. The oscillator may operate in either high-speed or low-speed mode. Low-speed mode is intended ...
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Internal RC Oscillator The AT89LP428/828 has an Internal RC oscillator (IRC) tuned to 8.0 MHz ±1.0% at 5.0V and 25 C. When enabled as the clock source, XTAL1 and XTAL2 may be used as P4.0 and P4.1, ° respectively. ...
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Table 6-2. – Clock Control Register CLKREG CLKREG = 8FH Not Bit Addressable TPS3 TPS2 Bit 7 6 Symbol Function TPS [ Timer Prescaler. The Timer Prescaler selects the time base for Timer 0, Timer 1, Timer 2 ...
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Figure 7-1. Time-out Internal Internal Note: If the Brown-out Detector (BOD) is also enabled, the start-up timer does not begin counting until after V CC occurs prior to the end of the initialization sequence, the timer must first wait for ...
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Table 7-1. SUT Fuse 1 7.2 Brown-out Reset The AT89LP428/828 has an on-chip Brown-out Detector (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level V is nominally 2.2V. The ...
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External Reset The P3.6/RST pin can function as either an active-low reset input digital general- purpose I/O, P3.6. The Reset Pin Enable Fuse, when set to “1”, enables the external reset input function on P3.6. (see ...
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Power-down Mode Setting the Power-down (PD) bit in PCON enters Power-down mode. Power-down mode stops the oscillator, disables the BOD and powers down the Flash memory in order to minimize power consumption. Only the power-on circuitry will continue to ...
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Figure 8-2. 8.2.2 Reset Recovery from Power-down The wake-up from Power-down through an external reset is similar to the interrupt with PWDEX = “0”. At the falling edge of RST, Power-down is exited, the oscillator is restarted, and an internal ...
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Table 8-1. – Power Control Register PCON PCON = 87H Not Bit Addressable SMOD1 SMOD0 Bit 7 6 Symbol Function SMOD1 Double Baud Rate Bit. Doubles the baud rate of the UART in Modes SMOD0 Frame ...
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The Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1, which are set by a rollover in their respective Timer/Counter registers (except for Timer 0 in Mode 3). When a timer interrupt is generated, the on-chip hardware ...
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Interrupt Response Time The interrupt flags may be set by their hardware in any clock cycle. The interrupt controller polls the flags in the last clock cycle of the instruction in progress. If one of the flags was set ...
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Interrupt Registers Table 9-2. IE – Interrupt Enable Register IE = A8H Bit Addressable EA EC Bit 7 6 Symbol Function Global enable/disable. All interrupts are disabled when When each interrupt source is ...
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Table 9-4. IPH – Interrupt Priority High Register IPH = B7H Not Bit Addressable IP1D PCH Bit 7 6 Symbol Function IP1D Interrupt Priority 1 Disable. Set IP1D disable all interrupts with priority level one. Clear to ...
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Table 9-6. IP2 – Interrupt Priority 2 Register IP = B5H No Bit Addressable IP2D – Bit 7 6 Symbol Function IP2D Interrupt Priority 2 Disable. Set IP2D disable all interrupts with priority level two. Clear to ...
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I/O Ports The AT89LP428/828 can be configured for between 23 and 30 I/O pins. The exact number of I/O pins available depends on the package type and the clock and reset options as shown in Table 10-1. Table 10-1. ...
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Table 10-3. Port 10.1.1 Quasi-bidirectional Output Port pins in quasi-bidirectional output mode function similar to standard 8051 port pins. A Quasi- bidirectional port can be used both as an input and output without the need to reconfigure the port. This ...
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Input-only Mode The input only port configuration is shown in input includes a Schmitt-triggered input for improved input noise rejection. The input circuitry of P3.2, P3.3, P3.6, P4.0 and P4.1 is not disabled during Power-down (see fore these pins ...
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Push-pull Output The push-pull output configuration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic “1”. The push-pull mode may be ...
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Port Read-Modify-Write A read from a port will read either the state of the pins or the state of the port register depending on which instruction is used. Simple read instructions will always access the port pins directly. Read-modify-write ...
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Table 10-6. Port Pin P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P4.6 P4.7 AT89LP428/828 40 Port Pin Alternate Functions Configuration Bits PxM0.y PxM1.y P1M0.0 ...
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Enhanced Timer 0 and Timer 1 with PWM The AT89LP428/828 has two 16-bit Timer/Counters, Timer 0 and Timer 1, with the following features: • Two 16-bit timer/counters with 16-bit reload registers • Two independent 8-bit precision PWM outputs with ...
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Mode 0 – Variable Width Timer/Counter Both Timers in Mode 0 are 8-bit Counters with a variable prescaler. The prescaler may vary from bits depending on the PSC bits in TCONB, giving the timer a range ...
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Figure 11-2. Timer/Counter 1 Mode 1: 16-bit Auto-reload INT1 Pin 11.3 Mode 2 – 8-bit Auto-Reload Timer/Counter Mode 2 configures the Timer register as an 8-bit Counter (TL1) with automatic reload, as shown in Figure TH1, which is preset by ...
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Mode 3 – 8-bit Split Timer Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two separate counters. The ...
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Table 11-2. – Timer/Counter Control Register TCON TCON = 88H Bit Addressable TF1 TR1 Bit 7 6 Symbol Function Timer 1 Overflow Flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the processor vectors TF1 to interrupt routine. ...
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Table 11-3. TMOD – Timer/Counter Mode Control Register TMOD Address = 089H Not Bit Addressable GATE1 C/T1 Bit 7 6 Symbol Function Timer 1 Gating Control. When set. Timer/Counter 1 is enabled only while INT1 pin is high and TR1 ...
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Table 11-4. – Timer/Counter Control Register B TCONB TCONB = 91H Not Bit Addressable PWM1EN PWM0EN Bit 7 6 Symbol Function PWM1EN Configures Timer 1 for Pulse Width Modulation output on T1 (P3.5). PWM0EN Configures Timer 0 for Pulse Width ...
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Mode 0 – 8-bit PWM with 8-bit Logarithmic Prescaler In Mode 0, TLx acts as a logarithmic prescaler driving 8-bit counter THx (see PSCx bits in TCONB control the prescaler value. On THx overflow, the duty cycle value in ...
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Figure 11-7. Timer/Counter 1 PWM Mode 1 GATE INT1 Pin 11.5.3 Mode 2 – 8-bit Frequency Generator Timer 0 in PWM mode 2 functions as an 8-bit Auto-reload timer, the same as normal Mode 2, with the exception that the ...
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Figure 11-9. PWM Mode 2 Waveform 11.5.4 Mode 3 – Split 8-bit PWM Timer 1 in PWM mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in PWM mode 3 establishes ...
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Figure 11-10. Timer/Counter 0 PWM Mode 3 3654A–MICRO–8/09 ÷TPS OSC Control TR0 GATE INT0 Pin ÷TPS OSC TR1 AT89LP428/828 RL0 (8 Bits) OCR0 = T0 TL0 (8 Bits) RH0 (8 Bits) OCR1 = T1 TH0 (8 Bits) 51 ...
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Enhanced Timer 2 The AT89LP428/828 includes a 16-bit Timer/Counter 2 with the following features: • 16-bit timer/counter with one 16-bit reload/capture register • One external reload/capture input • Up/Down counting mode with external direction control • UART baud rate ...
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Timer 2 Registers Control and status bits for Timer 2 are contained in registers T2CON (see T2MOD (see 16-bit timer register for Timer 2. The register pair {RCAP2H, RCAP2L} at addresses 0CBH and 0CAH are the 16-bit Capture/Reload register ...
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Table 12-4. T2MOD – Timer 2 Mode Control Register T2MOD Address = 0C9H Not Bit Addressable PHSD PHS2 Bit 7 6 Symbol Function PHSD CCA Phase Direction. For phase modes with channels, PHSD determines the direction that ...
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Capture Mode In the Capture mode, Timer fixed 16-bit timer or counter that counts up from MIN to MAX. An overflow from MAX to MIN sets bit TF2 in T2CON. If EXEN2 = 1, a 1-to-0 ...
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Up Counter Figure 12-2 this mode Timer 2 counts up to MAX and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with BOTTOM, the 16-bit value in RCAP2H and RCAP2L. ...
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Figure 12-3. Timer 2 Waveform: Auto-reload Mode (DCEN = 0) 12.3 Down Counter Setting DCEN = 1 enables Timer 2 to count up or down, as shown in the T2EX pin controls the direction of the count (if ...
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The timer overflow/underflow rate for up-down counting mode is the same as for up counting mode, provided that the count direction does not change. Changes to the count direction may result in longer or shorter periods between time-outs. Figure 12-5. ...
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Figure 12-6. Timer 2 Waveform: Dual Slope Modes 12.4 Baud Rate Generator Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON 12-3 on page used for the receiver or transmitter and Timer 1 ...
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Timer baud rate generator is shown in TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2 and will not generate an inter- rupt. Note too, that if EXEN2 is set, a ...
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Figure 12-8. Timer 2 in Clock-out Mode 13. Compare/Capture Array The AT89LP428/828 includes a four channel Compare/Capture Array (CCA) that performs a variety of timing operations including input event capture, output compare waveform generation and pulse width modulation (PWM). Timer ...
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Timer 2 must be running (TR2 = 1) in order to perform captures or compares with the CCA. However, when TR2 = 0 the external capture events will still set their associated flags and may be used as additional external ...
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Table 13-1. T2CCA – Timer/Counter 2 Compare/Capture Address T2CCA Address = 0D1H Not Bit Addressable – – Bit 7 6 Symbol Function Compare/Capture Address. Selects which CCA channel is currently accessible through the T2CCH, T2CCL and T2CCC registers. Only one ...
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Table 13-4. T2CCC – Timer/Counter 2 Compare/Capture Control T2CCC Address = 0D4H Not Bit Addressable CIENx CDIRx Bit 7 6 Symbol Function CIENx Channel X Interrupt Enable. When set, channel X’s interrupt flag, CCFx in T2CCF, will generate an interrupt ...
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Table 13-5. T2CCF – Timer/Counter 2 Compare/Capture Flags T2CCF Address = 0D5H Not Bit Addressable – – Bit 7 6 Symbol Function Channel D Compare/Capture Interrupt Flag. Set by a compare/capture event on channel D. Must be cleared by software. ...
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Each CCA channel has an associated external capture input pin: CCA (P2.0), CCB (P2.1), CCC (P2.2) and CCD (P2.3). External capture events are always edge-triggered and can be selected to occur at a negative edge, positive edge, or both (toggle). ...
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Waveform Generation Each CCA channel has an associated external compare output pin: CCA (P2.0), CCB (P2.1), CCC (P2.2) and CCD (P2.3). The CxM compare event occurs. The output pin may be set to 1, cleared toggled. ...
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Figure 13-5. CTC Mode Waveform Example 13.3.1.3 Dual-Slope Mode The dual-slope mode occurs when CP/RL2 = 0 and T2CM of the output is determined by the TOP value stored in RCAP2L and RCAP2H and output edges occur at fractions of ...
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TOP value of the timer. The CCA PWM always uses the greatest precision allowable for the selected output frequency, as compared to Timer 0 and 1 whose PWMs are fixed at 8-bit precision ...
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Figure 13-8. Asymmetrical (Edge-Aligned) PWM {RCAP2H,RCA2L} 13.4.2 Symmetrical PWM For Symmetrical PWM, Timer 2 should be configured for Auto-reload mode and Count Mode (CP/RL2 = 0, DCEN = 0, T2CM1-0 = 1xB). Symmetrical PWM uses dual-slope operation ...
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Figure 13-9. Non-overlapping Waveforms Using Symmetrical PWM {RCAP2H,RCA2L} {CCAH,CCAL} {CCBH,CCBL} (Inverted) CCA (Non-Inverted) CCB 13.4.2.1 Phase and Frequency Correct PWM When T2CM this mode the compare value double buffer is only updated when the timer equals MIN (under- flow). This ...
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Figure 13-11. Phase Correct Symmetrical (Center-Aligned) PWM {RCAP2H,RCA2L} {CCxH,CCxL} Non-Inverted 13.4.3 Multi-Phasic PWM The PWM channels may be configured to provide multi-phasic alternating outputs by the PHS bits in T2MOD. The AT89LP428/828 provides 1 out out of ...
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Figure 13-12. Multi-Phasic PWM Output Stage PHS = 001B CCA 1 EN CCB 0 EN CCC 1 EN CCD 1 EN Figure 13-13. Multi-Phasic PWM Modes CCA CCB CCC CCD CCA CCB CCC CCD CCA CCB CCC CCD PHSD CCA ...
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Figure 13-14. Three-Phase Mode with Channel B Disabled CCA CCB CCC PHSD 14. External Interrupts The INT0 (P3.2) and INT1 (P3.3) pins of the AT89LP428/828 may be used as external interrupt sources. The external interrupts can be programmed to be ...
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Figure 15-1. GPI Block Diagram GPLS 1 (P1.7) GPI7 0 1 (P1.6) GPI6 0 1 (P1.5) GPI5 0 1 (P1.4) GPI4 0 1 (P1.3) GPI3 0 1 (P1.2) GPI2 0 1 (P1.1) GPI1 0 1 (P1.0) GPI0 0 . Table ...
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Table 15-2. – General-purpose Interrupt Level Select Register GPLS GPLS = 9BH Not Bit Addressable GPLS7 GPLS6 Bit 7 6 GPMOD detect low level or negative edge on P1 detect high level or positive edge on ...
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Serial Interface (UART) The serial interface on the AT89LP428/828 implements a Universal Asynchronous Receiver/Transmitter (UART). The UART has the following features: • Full-duplex Operation • Data Bits • Framing Error Detection • Multiprocessor Communication Mode with ...
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An address byte, however, interrupts all slaves. Each slave can examine the received byte and see being addressed. The addressed slave clears its SM2 bit and prepares to receive the data bytes ...
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Baud Rates The baud rate in Mode 0 depends on the value of the SMOD1 bit in Special Function Register PCON.7. If SMOD1 = 0 (the value on reset) and TB8 = 0, the baud rate is 1/4 of ...
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Programmers can achieve very low baud rates with Timer 1 by configuring the Timer to run as a 16-bit auto-reload timer (high nibble of TMOD = 0001B). In this case, the baud rate is given by the following formula. Table ...
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Table 16-3. Baud Rate 16.3 More About Mode 0 In Mode 0, the UART is configured as a 2-wire half-duplex synchronous serial interface. Serial data enters and exits through RXD. TXD outputs the shift clock. Eight data bits are transmit- ...
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Reception is initiated by the condition REN = 1 and the next clock cycle, the RX Con- trol unit writes the bits 11111110 to the receive shift register and activates RECEIVE in the next clock phase. ...
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Figure 16-1. Serial Port Mode 0 TIMER 1 OVERFLOW f osc 1 0 TB8 ÷2 ÷ SMOD1 WRITE TO SBUF SEND SHIFT RXD (DATA OUT) TXD (SHIFT CLOCK) TI WRITE TO SCON (CLEAR RI) RI RECEIVE SHIFT RXD ...
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Figure 16-2. Mode 0 Waveforms SMOD1 = 0 SM2 = 0 SMOD1 = 1 SM2 = 0 SMOD1 = 0 SM2 = 1 SMOD1 = 1 SM2 = 1 Mode 0 may be used as a hardware accelerator for software ...
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More About Mode 1 Ten bits are transmitted (through TXD), or received (through RXD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in SCON. In ...
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Figure 16-4. Serial Port Mode 1 TIMER 1 TIMER 2 OVERFLOW OVERFLOW WRITE TO ÷2 SBUF “0” “1” SMOD1 “0” “1” TCLK “0” “1” INTERRUPT RCLK SAMPLE 1-TO-0 TRANSITION DETECTOR RXD TX CLOCK WRITE TO SBUF SEND DATA SHIFT D0 ...
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More About Modes 2 and 3 Eleven bits are transmitted (through TXD), or received (through RXD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the 9th ...
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Figure 16-5. Serial Port Mode 2 CPU CLOCK SMOD1 1 SMOD1 0 AT89LP428/828 88 INTERNAL BUS INTERNAL BUS 3654A–MICRO–8/09 ...
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Figure 16-6. Serial Port Mode 3 TIMER 1 TIMER 2 OVERFLOW OVERFLOW WRITE TO ÷2 SBUF “0” “1” SMOD1 “0” “1” TCLK “0” “1” INTERRUPT RCLK SAMPLE 1-TO-0 TRANSITION DETECTOR RXD TX CLOCK WRITE TO SBUF SEND DATA SHIFT D0 ...
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Framing Error Detection In addition to all of its usual modes, the UART can perform framing error detection by looking for missing stop bits, and automatic address recognition. When used for framing error detect, the UART looks for missing ...
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In a more complex system, the following could be used to select slaves 1 and 2 while excluding slave 0: Slave 0 Slave 1 Slave 2 In the above example, the differentiation among the 3 slaves is in the lower ...
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Figure 17-1. SPI Block Diagram T1 OVF ÷4/÷8/÷32/÷64 The interconnection between master and slave CPUs with SPI is shown in pins in the interface are Master-In/Slave-Out (MISO), Master-Out/Slave-In (MOSI), Shift Clock (SCK), and Slave Select (SS). The SCK pin is ...
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Figure 17-2. SPI Master-Slave Interconnection When the SPI is configured as a Master (MSTR in SPCR is set), the operation of the SS pin depends on the setting of the Slave Select Ignore bit, SSIG. If SSIG = 1, the ...
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While the TXE flag is set, the transmit buffer is empty. TXE can be cleared by software or by writing to SPDR. Writing to SPDR will clear TXE and load the transmit buffer. The user may load the buffer while ...
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Pin Configuration When the SPI is enabled (SPE = 1), the data direction of the MOSI, MISO, SCK, and SS pins is automatically overridden according to the MSTR bit as shown in need to reconfigure the pins when switching ...
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Serial Clock Timing The TSCK, CPHA, CPOL and SPR bits in SPCR control the shape and rate of SCK. The two SPR bits provide four possible bit clock rates when the SPI is in master mode. The TSCK bit ...
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SPI Registers Table 17-2. SPDR – SPI Data Register SPDR Address = EAH Not Bit Addressable SPD7 SPD6 Bit 7 6 Writes to SPDR load the transmit buffer. In Master mode, a write also starts a transfer if the ...
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Table 17-4. SPSR – SPI Status Register SPSR Address = E8H Not Bit Addressable SPIF WCOL Bit 7 6 Symbol Function SPI Transfer Complete Interrupt Flag. When a serial transfer is complete, the SPIF bit is set by hardware and ...
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The corresponding comparator interrupt should not be enabled during that time, and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an ...
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Analog Input Muxes The positive input terminal of each comparator may be connected to any of the four analog input pins by changing the CSA input pins, the comparator must be disconnected from its inputs by clearing the CONA ...
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Figure 18-3. Dual Comparator Configuration Examples a. dual independent comparators with external references + AIN0 A - AIN1 CSA = 00 RFA = 00 b. 3-channel comparator with external reference AIN0 AIN2 AIN1 AIN3 CSA = 00/10/11 RFA = 00 ...
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Table 18-1. – Analog Comparator a Control and Status Register ACSRA ACSRA = 97H Not Bit Addressable CSA1 CSA0 Bit 7 6 Symbol Function CSA Comparator A Positive Input Channel Select [ CSA1 CSA0 A+ Channel 0 0 ...
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Table 18-2. – Analog Comparator B Control and Status Register ACSRB ACSRB = 9FH Not Bit Addressable CSB1 CSB0 Bit 7 6 Symbol Function CSB Comparator B Positive Input Channel Select [ CSB1 CSB0 ...
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Table 18-3. – Analog Comparator Reference Control Register AREF AREF = AFH Not Bit Addressable CBC1 CBC0 Bit 7 6 Symbol Function CSC Comparator B Clock Select [ CBC1 CBC0 Clock Source 0 0 System Clock 0 0 ...
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Programmable Watchdog Timer The programmable Watchdog Timer (WDT) protects the system from incorrect execution by trig- gering a system reset when it times out after the software has failed to feed the timer prior to the timer overflow. By ...
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Software Reset A Software Reset of the AT89LP428/828 is accomplished by writing the software reset sequence 5AH/A5H to the WDTRST SFR. The WDT does not need to be enabled to generate the software reset. A normal software reset will ...
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Instruction Set Summary The AT89LP428/828 is fully binary compatible with the MCS-51 instruction set. The difference between the AT89LP428/828 and the standard 8051 is the number of cycles required to execute an instruction. Instructions in the AT89LP428/828 may take ...
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Table 20-1. MUL AB DIV Logical CLR A CPL A ANL A, Rn ANL A, direct ANL A, @Ri ANL A, #data ANL direct, A ANL direct, #data ORL A, Rn ORL A, direct ORL A, @Ri ...
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Table 20-1. MOV direct, A MOV direct, Rn MOV direct, direct MOV direct, @Ri MOV direct, #data MOV @Ri, A MOV @Ri, direct MOV @Ri, #data MOV DPTR, #data16 MOV /DPTR, #data16 MOVC A, @A+DPTR MOVC A, @A+/DPTR MOVC A, ...
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Table 20-1. Branching JC rel JNC rel JB bit, rel JNB bit, rel JBC bit, rel JZ rel JNZ rel SJMP rel ACALL addr11 LCALL addr16 RET RETI AJMP addr11 LJMP addr16 JMP @A+DPTR JMP @A+PC CJNE A, direct, rel ...
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Register Index Table 21-1. Name ACC ACSRA ACSRB AREF B CLKREG DPCF (AUXR1) DPH0 DPH1 DPL0 DPL1 GPIEN GPIF GPLS GPMOD IE IE2 IP IP2 IPH IP2H MEMCON P1 P1M0 P1M1 P2 P2M0 P2M1 P3 P3M0 P3M1 P4 P4M0 ...
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Table 21-1. PSW RCAP2H RCAP2L RH0 RH1 RL0 RL1 SADDR SADEN SBUF SCON SP SPCR SPDR SPSR T2CCA T2CCC T2CCF T2CCH T2CCL T2CON T2MOD TCON TCONB TH0 TH1 TH2 TL0 TL1 TL2 TMOD WDTCON WDTRST AT89LP428/828 112 Special Function Register ...
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On-chip Debug System The AT89LP428/828 On-chip Debug (OCD) System uses a 2-wire serial interface to control pro- gram flow; read, modify, and write the system state; and program the nonvolatile memory. The OCD System has the following features: • ...
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Figure 22-1. AT89LP428/828 On-chip Debug Connections 22.2 Software Breakpoints The AT89LP428/828 microcontroller includes a BREAK instruction for implementing program memory breakpoints in software. A software breakpoint can be inserted manually by placing the BREAK instruction in the program code. Some ...
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Programming the Flash Memory The Atmel AT89LP428/828 microcontroller features 4K/8K bytes of on-chip In-System Program- mable Flash program memory and 512/1024 bytes of nonvolatile Flash data memory. In-System Programming allows programming and reprogramming of the microcontroller positioned inside the ...
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... Fuse Write with Auto-Erase command using the temporary data. Lock bits are treated in a simi- lar manner to fuses except they may only be erased (unlocked) by Chip Erase. Table 23-1. Device # AT89LP428 AT89LP828 AT89LP428/828 116 Tables 23-1 and 23-2 Code Memory Size Code Size ...
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... Table 23-2. Device # AT89LP428 AT89LP828 Figure 23-2. AT89LP428/828 Memory Organization 23.3 Command Format Programming commands consist of an opcode byte, two address bytes, and zero or more data bytes. In addition, all command packets must start with a two-byte preamble of AAH and 55H. The preamble increases the noise immunity of the programming interface by making it more dif- ficult to issue unintentional commands ...
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After each data byte has been transmitted, the byte address is incremented to point to the next data byte. This allows a page command to linearly sweep the bytes within a page. If the byte address is incremented ...
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... Each byte address selects one fuse or lock bit. Data bytes must be 00H or FFH. 4. See Table 23-6 on page 121 5. See Table 23-5 on page 120 6. Atmel Signature Bytes: Address: 0000H AT89LP428: 1EH AT89LP828: 1EH 7. Symbol Key: a: Page Address Bit b: Byte Address Bit x: Don’t Care Bit 3654A–MICRO–8/09 ...
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Status Register The current state of the memory may be accessed by reading the status register. The status reg- ister is shown in Table 23-4. Bit Symbol LOAD SUCCESS WRTINH BUSY 23.5 DATA Polling The AT89LP428/828 implements DATA polling ...
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User Configuration Fuses The AT89LP428/828 includes 11 user fuses for configuration of the device. Each fuse is accessed at a separate address in the User Fuse Row as listed in by programming 00H to their locations. Programming FFH to ...
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User Signature and Analog Configuration The User Signature Array contains 128 bytes of nonvolatile memory in two 64-byte pages. The first page of the User Signature Array (0000H - 003FH) is available for serial numbers, firmware revision information, date ...
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Figure 23-5. Serial Programming Power-up Sequence MISO MOSI 23.9.2 Power-down Sequence Execute this sequence to power-down the device after programming. 1. Drive SCK low. 2. Wait at least t 3. Tristate MOSI. 4. Wait at least t 5. Wait no ...
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ISP Start Sequence Execute this sequence to exit CPU execution mode and enter ISP mode when the device has passed Power-on Reset and is already operational. 1. Drive RST low. 2. Drive SS high. 3. Wait t 4. Start ...
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Serial Peripheral Interface The Serial Peripheral Interface (SPI byte-oriented full-duplex synchronous serial communi- cation channel. During In-System Programming, the programmer always acts as the SPI master and the target device always acts as the SPI slave. The ...
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Timing Parameters The timing parameters for are shown in Table 23-8. Symbol t CLCL t PWRUP t POR t PWRDN t RLZ t STL t RHZ t SCK t SHSL t SLSH SIS t ...
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Electrical Characteristics 24.1 Absolute Maximum Ratings* Operating Temperature ................................... -40°C to +85°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground......-0.7V to +5.5V Maximum Operating Voltage ............................................ 5.5V DC Output Current...................................................... 15.0 mA 24.2 ...
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Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as quasi-bidi- rectional (with internal pull-ups). A square wave generator with rail-to-rail output ...
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Supply Current (External Clock) Figure 24-3. Active Supply Current vs. Frequency Figure 24-4. Idle Supply Current vs. Frequency 3654A–MICRO–8/ Frequency (MHz ...
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Crystal Oscillator Figure 24-5. Quartz Crystal Input at 5V Figure 24-6. Ceramic Resonator Input at 5V AT89LP428/828 130 Oscillator Amplitude vs. Frequency Quartz Crystal with R1 = 4MΩ ...
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Quasi-Bidirectional Input Figure 24-7. Quasi-bidirectional Input Transition Current at 5V Figure 24-8. Quasi-bidirectional Input Transition Current at 3V 3654A–MICRO–8/09 0.0 0.5 1.0 1.5 2.0 2.5 0 -50 -100 -150 -200 V IL 0.0 0.5 1.0 1.5 0 -20 -40 ...
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Clock Characteristics The values shown in this table are valid for T Figure 24-9. External Clock Drive Waveform Table 24-1. External Clock Parameters Symbol Parameter 1/t Oscillator Frequency CLCL t Clock Period CLCL t External Clock High Time CHCX ...
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Serial Peripheral Interface Timing The values shown in this table are valid for T Table 24-4. SPI Master Characteristics Symbol Parameter t Oscillator Period CLCL t Serial Clock Cycle Time SCK t Clock High Time SHSL t Clock Low ...
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Figure 24-10. SPI Master Timing (CPHA = 0) SS SCK (CPOL = 0) SCK (CPOL = 1) MISO MOSI Figure 24-11. SPI Slave Timing (CPHA = 0) SS SCK (CPOL = 0) SCK (CPOL= 1) MISO MOSI Figure 24-12. SPI ...
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Figure 24-13. SPI Slave Timing (CPHA = 1) SS SCK (CPOL = 0) SCK (CPOL = 1) MISO MOSI 24.7 Dual Analog Comparator Characteristics The values shown in this table are valid for T Table 24-6. Dual Analog Comparator Characteristics ...
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Serial Port Timing: Shift Register Mode The values in this table are valid for V Symbol Parameter t Serial Port Clock Cycle Time XLXL t Output Data Setup to Clock Rising Edge QVXH t Output Data Hold after Clock ...
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I Test Condition, Active Mode, All Other Pins are Disconnected CC 24.9.4 I Test Condition, Idle Mode, All Other Pins are Disconnected CC 24.9.5 Clock Signal Waveform for 0.5V CC 0.45V 24.9.6 I Test Condition, Power-down ...
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... AT89LP828-20PU AT89LP828-20JU AT89LP828-20MU AT89LP428-25AU AT89LP428-25PU AT89LP428-25JU AT89LP428-25MU 25 4.0V to 5.5V AT89LP828-25AU AT89LP828-25PU AT89LP828-25JU AT89LP828-25MU 32A 32-lead, Thin Plastic Quad Flat Package (TQFP) 28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP) 32J 32-lead, Plastic J-leaded Chip Carrier (PLCC) 32M1-A 32-pad x1.0 mm Body, Lead Pitch 0.5 mm, Micro Lead Frame Package (MLF) ...
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Packaging Information 26.1 32A – TQFP PIN 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per ...
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PDIP A SEATING PLANE Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 ...
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PLCC 1.14(0.045) X 45˚ 0.51(0.020)MAX 45˚ MAX (3X) Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per ...
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MLF Pin TOP VIEW Pin #1 Notch (0. BOTTOM VIEW Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2. 2325 Orchard Parkway San Jose, ...
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Revision History Revision No. Revision A – August 2009 3654A–MICRO–8/09 History • Initial Release AT89LP428/828 143 ...
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AT89LP428/828 144 3654A–MICRO–8/09 ...
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Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 2 Overview ................................................................................................... 5 3 Memory Organization .............................................................................. 8 4 Special Function Registers ................................................................... 15 5 Enhanced CPU ....................................................................................... 16 6 System Clock ......................................................................................... 20 7 Reset ....................................................................................................... 23 3654A–MICRO–8/09 1.1 28P3 ...
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Power Saving Modes ............................................................................. 26 8.1 Idle Mode .........................................................................................................26 8.2 Power-down Mode ...........................................................................................27 9 Interrupts ................................................................................................ 29 9.1 Interrupt Response Time .................................................................................31 9.2 Interrupt Registers ...........................................................................................32 10 I/O Ports .................................................................................................. 35 10.1 Port Configuration ............................................................................................35 10.2 Port 2 Analog ...
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Enhanced Serial Peripheral Interface .................................................. 91 18 Dual Analog Comparators ..................................................................... 98 19 Programmable Watchdog Timer ......................................................... 105 20 Instruction Set Summary .................................................................... 107 21 Register Index ...................................................................................... 111 22 On-chip Debug System ....................................................................... 113 23 Programming the Flash ...
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User Signature and Analog Configuration .....................................................122 23.9 Programming Interface Timing ......................................................................122 24 Electrical Characteristics .................................................................... 127 24.1 Absolute Maximum Ratings* .........................................................................127 24.2 DC Characteristics .........................................................................................127 24.3 Typical Characteristics ..................................................................................128 24.4 Clock Characteristics .....................................................................................132 24.5 Reset Characteristics ....................................................................................132 24.6 Serial ...
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... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2009 Atmel Corporation. All rights reserved. Atmel Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Asia Atmel Europe ...