AT89LP828 Atmel Corporation, AT89LP828 Datasheet - Page 22

• Manufacturer Part Number: AT89LP828
• Manufacturer: Atmel Corporation

Specifications of AT89LP828

• Flash (kbytes): 8 Kbytes
• Max. Operating Frequency: 25 MHz
• Cpu: 8051-1C
• Max I/o Pins: 30
• Spi: 1
• Uart: 1
• Sram (kbytes): 0.75
• Eeprom (bytes): 1024
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

6.3
6.4
6.5
22
Internal RC Oscillator
System Clock Out
System Clock Divider
AT89LP428/828
The AT89LP428/828 has an Internal RC oscillator (IRC) tuned to 8.0 MHz ±1.0% at 5.0V and
25
respectively. XTAL2 may also be configured to output a divided version of the system clock. The
frequency of the oscillator may be adjusted within limits by changing the RC Calibration Byte
stored at byte 64 of the User Signature Array. This location may be updated using the IAP inter-
face (location 00C0H in SIG space) or by an external device programmer (UROW location
0040H).
When the AT89LP428/828 is configured to use either an external clock or the internal RC oscil-
lator, the system clock divided by 2 may be output on XTAL2 (P4.1). The clock out feature is
enabled by setting the COE bit in CLKREG. For example, setting COE = “1” when using the
internal oscillator will result in a 4.0 MHz clock output on P4.1. P4.1 must be configured as an
output in order to use the clock out feature.
The CDV
source by powers of 2. The clock divider provides users with a greater frequency range when
using the Internal RC Oscillator. For example, to achieve a 1 MHz system frequency when using
the IRC, CDV
reduce power consumption by decreasing the operational frequency during non-critical periods.
The resulting system frequency is given by the following equation:
where f
for the CPU and all peripherals. The value of CDV may be changed at any time without interrupt-
ing normal execution. Changes to CDV are synchronized such that the system clock will not
pass through intermediate frequencies. When CDV is updated, the new frequency will take
affect within a maximum period of 32 x t
°
C. When enabled as the clock source, XTAL1 and XTAL2 may be used as P4.0 and P4.1,
OSC
See “User Signature and Analog Configuration” on page 122.
2-0
is the frequency of the selected clock source. The clock divider will prescale the clock
bits in CLKREG allow the system clock to be divided down from the selected clock
2-0
should be set to 011B for divide-by-8 operation. The divider can also be used to
OSC
f
SYS
.
=
------------ -
2
f
OSC
CDV
3654A–MICRO–8/09