AT89LP828 Atmel Corporation, AT89LP828 Datasheet - Page 100

• Manufacturer Part Number: AT89LP828
• Manufacturer: Atmel Corporation

Specifications of AT89LP828

• Flash (kbytes): 8 Kbytes
• Max. Operating Frequency: 25 MHz
• Cpu: 8051-1C
• Max I/o Pins: 30
• Spi: 1
• Uart: 1
• Sram (kbytes): 0.75
• Eeprom (bytes): 1024
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 3
• Isp: SPI/OCD
• Watchdog: Yes

18.1
18.2
18.3
100
Analog Input Muxes
Internal Reference Voltage
Comparator Interrupt Debouncing
AT89LP428/828
The positive input terminal of each comparator may be connected to any of the four analog input
pins by changing the CSA
input pins, the comparator must be disconnected from its inputs by clearing the CONA or CONB
bits. The connection is restored by setting the bits again after the muxes have been modified.
The corresponding comparator interrupt should not be enabled while the inputs are being
changed, and the comparator interrupt flag must be cleared before the interrupt is re-enabled in
order to prevent an unintentional interrupt request.
The negative input terminal of each comparator may be connected to an internal voltage refer-
ence by changing the RFB
set to 1.25V ±5%. The voltage reference also provides two additional voltage levels approxi-
mately 125 mV above and below V
as an internally referenced window comparator with up to four input channels. Changing the ref-
erence input must follow the same routine used for changing the positive input as described in
the
The comparator output is normally sampled every clock cycle. The conditions on the analog
inputs may be such that the comparator output will toggle excessively. This is especially true if
applying slow moving analog inputs. Three debouncing modes are provided to filter out this
noise for edge-triggered interrupts. In debouncing mode, the comparator uses Timer 1 to modu-
late its sampling time when CxC
waits until two Timer 1 overflows have occurred before resampling the output. If the new sample
agrees with the expected value, CFx is set. Otherwise, the event is ignored. The filter may be
tuned by adjusting the time-out period of Timer 1. Because Timer 1 is running free, the
debouncer must wait for two overflows to guarantee that the sampling delay is at least 1 time-out
period. Therefore, after the initial edge event, the interrupt may occur between 1 and 2 time-out
periods later. See
flows, i.e. CxC
be accepted as an edge event.
Figure 18-2. Negative Edge with Debouncing Example
“Analog Input Muxes”
SETB
CLR
ANL
...
ORL
ANL
EC
ACSRA, #0DFh ; Clear CONA to disconnect COMP A
ACSRA, #020h ; Set CONA to connect COMP A
ACSRA, #0EFh ; Clear any spurious interrupt
EC
1-0
Timer 1 Overflow
Comparator Out
= 00B, any change in the comparator output must be valid after 4 samples to
Figure
18-2. When the comparator clock is provided by one of the timer over-
section.
CFx
1-0
1-0
; Disable comparator interrupts
; Modify CSA or RFA bits
; Re-enable comparator interrupts
or CSB
Start
or RFA
1-0
AREF
= 00B. When a relevant transition occurs, the comparator
1-0
1-0
. These levels may be used to configure the comparators
bits in ACSRA and ACSRB. When changing the analog
bits in AREF. The internal reference voltage, V
(rejected)
Compare
Start
(accepted)
Compare
3654A–MICRO–8/09
AREF
, is