AT90PWM316 Atmel Corporation, AT90PWM316 Datasheet - Page 176
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AT90PWM316
Manufacturer Part Number
AT90PWM316
Description
Manufacturer
Atmel Corporation
Specifications of AT90PWM316
Flash (kbytes)
16 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
27
Ext Interrupts
4
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
3
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 105
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
1
Pwm Channels
12
32khz Rtc
No
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT90PWM316-16MU
Manufacturer:
SEAGATE
Quantity:
264
Part Number:
AT90PWM316-16MU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
AT90PWM316-16MUR
Manufacturer:
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Quantity:
20 000
Part Number:
AT90PWM316-16SU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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17. Serial Peripheral Interface – SPI
17.1
7710F–AVR–09/11
Features
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the
AT90PWM216/316 and peripheral devices or between several AVR devices.
The AT90PWM216/316 SPI includes the following features:
•
•
•
•
•
•
•
•
Figure 17-1. SPI Block Diagram
Note:
The interconnection between Master and Slave CPUs with SPI is shown in
tem consists of two shift Registers, and a Master clock generator. The SPI Master initiates the
communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and
Full-duplex, Three-wire Synchronous Data Transfer
Master or Slave Operation
LSB First or MSB First Data Transfer
Seven Programmable Bit Rates
End of Transmission Interrupt Flag
Write Collision Flag Protection
Wake-up from Idle Mode
Double Speed (CK/2) Master SPI Mode
1. Refer to
/2/4/8/16/32/64/128
DIVIDER
clk
Figure 3-1 on page
IO
(1)
3, and
Table 11-3 on page 68
AT90PWM216/316
for SPI pin placement.
Figure
17-2. The sys-
SPIPS
SS_A
MISO
MISO
_A
MOSI
MOSI
_A
SCK
_A
176
SCK
SS
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