AT90PWM316 Atmel Corporation, AT90PWM316 Datasheet - Page 29

• Manufacturer Part Number: AT90PWM316
• Manufacturer: Atmel Corporation

Specifications of AT90PWM316

• Flash (kbytes): 16 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 105
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 1
• Pwm Channels: 12
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

7.1.3
7.1.4
7.1.5
7.2
7710F–AVR–09/11
Clock Sources
Flash Clock – clk
PLL Clock – clk
ADC Clock – clk
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-
taneously with the CPU clock.
The PLL clock allows the PSC modules to be clocked directly from a 64/32 MHz clock. A 16 MHz
clock is also derived for the CPU.
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks
in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion
results.
The device has the following clock source options, selectable by Flash Fuse bits as illustrated by
Table 7-1
the appropriate modules.
Table 7-1.
The various choices for each clocking option is given in the following sections. When the CPU
wakes up from Power-down or Power-save, the selected clock source is used to time the start-
up, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts
from reset, there is an additional delay allowing the power to reach a stable level before starting
normal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up
time. The number of WDT Oscillator cycles used for each time-out is shown in
PLL
ADC
Device Clocking Option
External Crystal/Ceramic Resonator
PLL output divided by 4 : 16 MHz / PLL driven by External
Crystal/Ceramic Resonator
PLL output divided by 4 : 16 MHz / PLL driven by External
Crystal/Ceramic Resonator
Reserved
PLL output divided by 4 : 16 MHz
Calibrated Internal RC Oscillator
PLL output divided by 4 : 16 MHz / PLL driven by External
clock
External Clock
FLASH
1.For all fuses “1” means unprogrammed while “0” means programmed
2.Ext Osc : External Osc
3.RC Osc : Internal RC Oscillator
4.Ext Clk : External Clock Input
The clock from the selected source is input to the AVR clock generator, and routed to
Device Clocking Options Select AT90PWM216/316
System
Clock
Ext Osc
Ext Osc
PLL / 4
N/A
PLL / 4
RC Osc
PLL / 4
Ext Clk
AT90PWM216/316
(2)
PLL Input
RC Osc
Ext Osc
Ext Osc
N/A
RC Osc
RC Osc
Ext Clk
RC Osc
(4)
(3)
Table
1111 - 1000
0111- 0110
CKSEL3..0
0100
0101
0011
0010
0001
0000
7-2. The
(1)
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