ATmega165P Atmel Corporation, ATmega165P Datasheet - Page 235
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ATmega165P
Manufacturer Part Number
ATmega165P
Description
Manufacturer
Atmel Corporation
Specifications of ATmega165P
Flash (kbytes)
16 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
17
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATmega165PV-8AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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23.5.2
23.5.3
8019K–AVR–11/10
Scanning the RESET Pin
Scanning the Clock Pins
The RESET pin accepts 5V active low logic for standard reset operation, and 12V active high
logic for High Voltage Parallel programming. An observe-only cell as shown in
inserted both for the 5V reset signal; RSTT, and the 12V reset signal; RSTHV.
Figure 23-5. Observe-only Cell
The AVR devices have many clock options selectable by fuses. These are: Internal RC Oscilla-
tor, External Clock, (High Frequency) Crystal Oscillator, Low-frequency Crystal Oscillator, and
Ceramic Resonator.
Figure 23-6
The Enable signal is supported with a general Boundary-scan cell, while the Oscillator/clock out-
put is attached to an observe-only cell. In addition to the main clock, the timer Oscillator is
scanned in the same way. The output from the internal RC Oscillator is not scanned, as this
Oscillator does not have external connections.
Figure 23-6. Boundary-scan Cells for Oscillators and Clock Options
From Digital Logic
shows how each Oscillator with external connection is supported in the scan chain.
Previous
From
Cell
ShiftDR
0
1
From System Pin
ClockDR
D
UpdateDR
Q
Next
Cell
To
D
G
Previous
From
Cell
Q
ShiftDR
EXTEST
0
1
0
1
XTAL1/TOSC1
ClockDR
ENABLE
Oscillator
D
FF1
Q
XTAL2/TOSC2
OUTPUT
Next
Cell
To
To System Logic
Previous
From
Cell
ShiftDR
0
1
ClockDR
ATmega165P
D
FF1
Q
Next
Cell
To
Figure 23-5
To System Logic
235
is
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