ATmega165P Atmel Corporation, ATmega165P Datasheet - Page 57

• Manufacturer Part Number: ATmega165P
• Manufacturer: Atmel Corporation

Specifications of ATmega165P

• Flash (kbytes): 16 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 17
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

11. External Interrupts
11.1
8019K–AVR–11/10
Pin Change Interrupt Timing
The External Interrupts are triggered by the INT0 pin or any of the PCINT15..0 pins. Observe
that, if enabled, the interrupts will trigger even if the INT0 or PCINT15..0 pins are configured as
outputs. This feature provides a way of generating a software interrupt. The pin change interrupt
PCI1 will trigger if any enabled PCINT15..8 pin toggles. Pin change interrupts PCI0 will trigger if
any enabled PCINT7..0 pin toggles. The PCMSK1 and PCMSK0 Registers control which pins
contribute to the pin change interrupts. Pin change interrupts on PCINT15..0 are detected asyn-
chronously. This implies that these interrupts can be used for waking the part also from sleep
modes other than Idle mode.
The INT0 interrupts can be triggered by a falling or rising edge or a low level. This is set up as
indicated in the specification for the External Interrupt Control Register A – EICRA. When the
INT0 interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as
the pin is held low. Note that recognition of falling or rising edge interrupts on INT0 requires the
presence of an I/O clock, described in
level interrupt on INT0 is detected asynchronously. This implies that this interrupt can be used
for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all
sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level
must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If
the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-
rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described
in
An example of timing of a pin change interrupt is shown in
Figure 11-1. Pin Change Interrupt
“System Clock and Clock Options” on page
PCINT(0)
clk
pcint_setflag
pcint_in_(n)
PCINT(n)
pcint_syn
pin_sync
pin_lat
PCIF
clk
LE
pin_lat
D
Q
pin_sync
PCINT(0) in PCMSK(x)
“Clock Systems and their Distribution” on page
pcint_in_(0)
26.
0
x
clk
Figure
pcint_syn
11-1.
ATmega165P
pcint_setflag
PCIF
26. Low
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