ATmega165P Atmel Corporation, ATmega165P Datasheet - Page 93

• Manufacturer Part Number: ATmega165P
• Manufacturer: Atmel Corporation

Specifications of ATmega165P

• Flash (kbytes): 16 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 17
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

13.9
13.9.1
8019K–AVR–11/10
Register Description
TCCR0A – Timer/Counter Control Register A
• Bit 7 – FOC0A: Force Output Compare A
The FOC0A bit is only active when the WGM00 bit specifies a non-PWM mode. However, for
ensuring compatibility with future devices, this bit must be set to zero when TCCR0A is written
when operating in PWM mode. When writing a logical one to the FOC0A bit, an immediate com-
pare match is forced on the Waveform Generation unit. The OC0A output is changed according
to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a strobe. Therefore it is
the value present in the COM0A1:0 bits that determines the effect of the forced compare.
A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0A as TOP.
The FOC0A bit is always read as zero.
• Bit 6, 3 – WGM01:0: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for the maximum (TOP)
counter value, and what type of waveform generation to be used. Modes of operation supported
by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and
two types of Pulse Width Modulation (PWM) modes. See
on page
Table 13-2.
Note:
• Bit 5:4 – COM0A1:0: Compare Match Output Mode
These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0
bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin
must be set in order to enable the output driver.
When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the
WGM01:0 bit setting.
Bit
0x24 (0x44)
Read/Write
Initial Value
Mode
0
1
2
3
1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions.
87.
WGM01
(CTC0)
However, the functionality and location of these bits are compatible with previous versions of
the timer.
0
0
1
1
Waveform Generation Mode Bit Description
FOC0A
W
7
0
WGM00
(PWM0)
WGM00
0
1
0
1
R/W
6
0
Timer/Counter Mode
of Operation
Normal
PWM, Phase Correct
CTC
Fast PWM
COM0A1
R/W
5
0
COM0A0
R/W
4
0
WGM01
R/W
3
0
TOP
0xFF
0xFF
OCR0A
0xFF
Table 13-2
()
CS02
R/W
2
0
Update of
OCR0A at
Immediate
TOP
Immediate
BOTTOM
and
ATmega165P
CS01
R/W
1
0
“Modes of Operation”
CS00
R/W
TOV0 Flag Set
on
MAX
BOTTOM
MAX
MAX
0
0
TCCR0A
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