ATmega16M1 Automotive Atmel Corporation, ATmega16M1 Automotive Datasheet - Page 232

• Manufacturer Part Number: ATmega16M1 Automotive
• Manufacturer: Atmel Corporation

Specifications of ATmega16M1 Automotive

• Flash (kbytes): 16 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 27
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Can: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 150
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 14
• Input Capture Channels: 1
• Pwm Channels: 10
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

18.2
18.3
232
Operation
Starting a Conversion
Atmel ATmega16/32/64/M1/C1
The ADC converts an analog input voltage to a 10-bit digital value through successive approx-
imation. The minimum value represents GND and the maximum value represents the voltage
on the AREF pin minus 1 LSB. Optionally, AV
connected to the AREF pin by writing to the REFSn bits in the ADMUX Register. The internal
voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve
noise immunity.
The analog input channel are selected by writing to the MUX bits in ADMUX. Any of the ADC
input pins, as well as GND and a fixed bandgap voltage reference, can be selected as single
ended inputs to the ADC.
The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference is
set by the REFS1 and REFS0 bits in ADMUX register, whatever the ADC is enabled or not.
The ADC does not consume power when ADEN is cleared, so it is recommended to switch off
the ADC before entering power saving sleep modes.
The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and
ADCL. By default, the result is presented right adjusted, but can optionally be presented left
adjusted by setting the ADLAR bit in ADMUX.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data
Registers belongs to the same conversion. Once ADCL is read, ADC access to Data Regis-
ters is blocked. This means that if ADCL has been read, and a conversion completed before
ADCH is read, neither register is updated and the result from the conversion is lost. When
ADCH is read, ADC access to the ADCH and ADCL Registers is re-enabled.
The ADC has its own interrupt which can be triggered when a conversion completes. The ADC
access to the Data Registers is prohibited between reading of ADCH and ADCL, the interrupt
will trigger even if the result is lost.
A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC.
This bit stays high as long as the conversion is in progress and will be cleared by hardware
when the conversion is completed. If a different data channel is selected while a conversion is
in progress, the ADC will finish the current conversion before performing the channel change.
Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering
is enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source
is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB (See description of the
ADTS bits for a list of the trigger sources). When a positive edge occurs on the selected trigger
signal, the ADC prescaler is reset and a conversion is started. This provides a method of start-
ing conversions at fixed intervals. If the trigger signal is still set when the conversion
completes, a new conversion will not be started. If another positive edge occurs on the trigger
signal during conversion, the edge will be ignored. Note that an interrupt flag will be set even if
the specific interrupt is disabled or the Global Interrupt Enable bit in SREG is cleared. A con-
version can thus be triggered without causing an interrupt. However, the interrupt flag must be
cleared in order to trigger a new conversion at the next interrupt event.
CC
or an internal 2.56V reference voltage may be
7647G–AVR–09/11