ATmega16M1 Automotive Atmel Corporation, ATmega16M1 Automotive Datasheet - Page 95

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ATmega16M1 Automotive

Manufacturer Part Number
ATmega16M1 Automotive
Description
Manufacturer
Atmel Corporation

Specifications of ATmega16M1 Automotive

Flash (kbytes)
16 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
27
Ext Interrupts
27
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Can
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 150
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
14
Input Capture Channels
1
Pwm Channels
10
32khz Rtc
No
Calibrated Rc Oscillator
Yes
12.5.1
12.6
12.6.1
12.6.2
7647G–AVR–09/11
Modes of Operation
Compare Output Mode and Waveform Generation
Normal Mode
Clear Timer on Compare Match (CTC) Mode
The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM
modes. For all modes, setting the COM0x1:0 = 0 tells the Waveform Generator that no action
on the OC0x Register is to be performed on the next compare match. For compare output
actions in the non-PWM modes refer to
Table 12-3 on page
A change of the COM0x1:0 bits state will have effect at the first compare match after the bits
are written. For non-PWM modes, the action can be forced to have immediate effect by using
the FOC0x strobe bits.
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins,
is defined by the combination of the Waveform Generation mode (WGM02:0) and Compare
Output mode (COM0x1:0) bits. The Compare Output mode bits do not affect the counting
sequence, while the Waveform Generation mode bits do. The COM0x1:0 bits control whether
the PWM output generated should be inverted or not (inverted or non-inverted PWM). For
non-PWM modes the COM0x1:0 bits control whether the output should be set, cleared, or tog-
gled at a compare match
For detailed timing information refer to
The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot-
tom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the
same timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like
a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow
interrupt that automatically clears the TOV0 Flag, the timer resolution can be increased by
software. There are no special cases to consider in the Normal mode, a new counter value
can be written anytime.
The Output Compare unit can be used to generate interrupts at some given time. Using the
Output Compare to generate waveforms in Normal mode is not recommended, since this will
occupy too much of the CPU time.
In Clear Timer on Compare or CTC mode (WGM02:0 = 2), the OCR0A Register is used to
manipulate the counter resolution. In CTC mode the counter is cleared to zero when the coun-
ter value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter,
hence also its resolution. This mode allows greater control of the compare match output fre-
quency. It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in
increases until a compare match occurs between TCNT0 and OCR0A, and then counter
(TCNT0) is cleared.
101, and for phase correct PWM refer to
(See “Compare Match Output Unit” on page
Atmel ATmega16/32/64/M1/C1
“Timer/Counter Timing Diagrams” on page
Table 12-2 on page
Figure
12-5. The counter value (TCNT0)
101. For fast PWM mode, refer to
Table 12-4 on page
94.).
102.
99.
95

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