ATmega8515 Atmel Corporation, ATmega8515 Datasheet - Page 133
![no-image](/images/manufacturer_photos/0/0/79/atmel_corporation_sml.jpg)
ATmega8515
Manufacturer Part Number
ATmega8515
Description
Manufacturer
Atmel Corporation
Specifications of ATmega8515
Flash (kbytes)
8 Kbytes
Pin Count
44
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
35
Ext Interrupts
3
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
3
Input Capture Channels
1
Pwm Channels
3
32khz Rtc
No
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA8515
Manufacturer:
ATMEL
Quantity:
5 510
Company:
Part Number:
ATMEGA8515
Manufacturer:
NS
Quantity:
5 510
Part Number:
ATMEGA8515
Manufacturer:
AT
Quantity:
20 000
Company:
Part Number:
ATmega8515-16AC
Manufacturer:
MOT
Quantity:
3 450
Part Number:
ATmega8515-16AC
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATmega8515-16AI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATmega8515-16AU
Manufacturer:
ATMEL
Quantity:
4 500
Part Number:
ATmega8515-16AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATmega8515-16PU
Manufacturer:
AT
Quantity:
20 000
SPI Status Register – SPSR
SPI Data Register – SPDR
2512K–AVR–01/10
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if
SPIE in SPCR is set and global interrupts are enabled. If SS is an input and is driven low
when the SPI is in Master mode, this will also set the SPIF Flag. SPIF is cleared by
hardware when executing the corresponding interrupt handling vector. Alternatively, the
SPIF bit is cleared by first reading the SPI Status Register with SPIF set, then accessing
the SPI Data Register (SPDR).
• Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer.
The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register
with WCOL set, and then accessing the SPI Data Register.
• Bit 5..1 – Res: Reserved Bits
These bits are reserved bits in the ATmega8515 and will always read as zero.
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when
the SPI is in Master mode (see Table 58). This means that the minimum SCK period will
be two CPU clock periods. When the SPI is configured as Slave, the SPI is only guaran-
teed to work at f
The SPI interface on the ATmega8515 is also used for Program memory and EEPROM
downloading or uploading. See page 193 for Serial Programming and verification.
The SPI Data Register is a read/write register used for data transfer between the Regis-
ter File and the SPI Shift Register. Writing to the register initiates data transmission.
Reading the register causes the Shift Register Receive buffer to be read.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
SPIF
MSB
R/W
R
X
7
0
osc
7
/4 or lower.
WCOL
R/W
R
X
6
0
6
R/W
R
X
5
–
0
5
R/W
R
4
–
0
4
X
R/W
3
–
R
0
3
X
R/W
R
X
2
–
0
2
ATmega8515(L)
R/W
R
X
1
–
0
1
SPI2X
R/W
LSB
R/W
X
0
0
0
Undefined
SPSR
SPDR
133