ATmega8515 Atmel Corporation, ATmega8515 Datasheet - Page 78
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ATmega8515
Manufacturer Part Number
ATmega8515
Description
Manufacturer
Atmel Corporation
Specifications of ATmega8515
Flash (kbytes)
8 Kbytes
Pin Count
44
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
35
Ext Interrupts
3
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
3
Input Capture Channels
1
Pwm Channels
3
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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Extended MCU Control
Register – EMCUCR
General Interrupt Control
Register – GICR
78
ATmega8515(L)
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the
corresponding interrupt mask are set. The level and edges on the external INT0 pin that
activate the interrupt are defined in Table 41. The value on the INT0 pin is sampled
before detecting edges. If edge or toggle interrupt is selected, pulses that last longer
than one clock period will generate an interrupt. Shorter pulses are not guaranteed to
generate an interrupt. If low level interrupt is selected, the low level must be held until
the completion of the currently executing instruction to generate an interrupt.
Table 41. Interrupt 0 Sense Control
• Bit 0 – ISC2: Interrupt Sense Control 2
The Asynchronous External Interrupt 2 is activated by the external pin INT2 if the SREG
I-bit and the corresponding interrupt mask in GICR are set. If ISC2 is written to zero, a
falling edge on INT2 activates the interrupt. If ISC2 is written to one, a rising edge on
INT2 activates the interrupt. Edges on INT2 are registered asynchronously. Pulses on
INT2 wider than the minimum pulse width given in Table 42 will generate an interrupt.
Shorter pulses are not guaranteed to generate an interrupt. When changing the ISC2
bit, an interrupt can occur. Therefore, it is recommended to first disable INT2 by clearing
its Interrupt Enable bit in the GICR Register. Then, the ISC2 bit can be changed. Finally,
the INT2 Interrupt Flag should be cleared by writing a logical one to its Interrupt Flag bit
(INTF2) in the GIFR Register before the interrupt is re-enabled.
Table 42. Asynchronous External Interrupt Characteristics
• Bit 7 – INT1: External Interrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and
ISC10) in the MCU General Control Register (MCUCR) define whether the External
Interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed. Activity
on the pin will cause an interrupt request even if INT1 is configured as an output. The
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Symbol
ISC01
t
INT
0
0
1
1
Parameter
Minimum pulse width for
asynchronous external interrupt
ISC00
0
1
0
1
SM0
R/W
INT1
R/W
7
0
7
0
Description
The low level of INT0 generates an interrupt request.
Any logical change on INT0 generates an interrupt request.
The falling edge of INT0 generates an interrupt request.
The rising edge of INT0 generates an interrupt request.
SRL2
R/W
INT0
R/W
6
0
6
0
SRL1
R/W
INT2
R/W
5
0
5
0
SRL0
R/W
4
0
R
4
–
0
SRW01
R/W
Condition
3
0
R
3
–
0
SRW00
R/W
2
0
R
2
–
0
Min
SRW11
IVSEL
R/W
R/W
1
0
1
0
Typ
50
ISC2
R/W
IVCE
R/W
0
0
0
0
2512K–AVR–01/10
Max
EMCUCR
GICR
Units
ns