ATmega8515 Atmel Corporation, ATmega8515 Datasheet - Page 84

• Manufacturer Part Number: ATmega8515
• Manufacturer: Atmel Corporation

Specifications of ATmega8515

• Flash (kbytes): 8 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 35
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 3
• Input Capture Channels: 1
• Pwm Channels: 3
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

Compare Match Output
Unit
Compare Output Mode and
Waveform Generation
84
ATmega8515(L)
The Compare Output mode (COM01:0) bits have two functions. The Waveform Genera-
tor uses the COM01:0 bits for defining the Output Compare (OC0) state at the next
Compare Match. Also, the COM01:0 bits control the OC0 pin output source. Figure 37
shows a simplified schematic of the logic affected by the COM01:0 bit setting. The I/O
Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the
general I/O port Control Registers (DDR and PORT) that are affected by the COM01:0
bits are shown. When referring to the OC0 state, the reference is for the internal OC0
Register, not the OC0 pin. If a System Reset occur, the OC0 Register is reset to “0”.
Figure 37. Compare Match Output Unit, Schematics
The general I/O port function is overridden by the output compare (OC0) from the Wave-
form Generator if either of the COM01:0 bits are set. However, the OC0 pin direction
(input or output) is still controlled by the Data Direction Register (DDR) for the port pin.
The Data Direction Register bit for the OC0 pin (DDR_OC0) must be set as output
before the OC0 value is visible on the pin. The port override function is independent of
the Waveform Generation mode.
The design of the output compare pin logic allows initialization of the OC0 state before
the output is enabled. Note that some COM01:0 bit settings are reserved for certain
modes of operation. See “8-bit Timer/Counter Register Description” on page 91.
The waveform generator uses the COM01:0 bits differently in Normal, CTC, and PWM
modes. For all modes, setting the COM01:0 = 0 tells the Waveform Generator that no
action on the OC0 Register is to be performed on the next Compare Match. For com-
pare output actions in the non-PWM modes refer to Table 45 on page 92. For fast PWM
mode, refer to Table 46 on page 92, and for phase correct PWM refer to Table 47 on
page 92.
A change of the COM01:0 bits state will have effect at the first Compare Match after the
bits are written. For non-PWM modes, the action can be forced to have immediate effect
by using the FOC0 strobe bits.
COMn1
COMn0
FOCn
clk
I/O
Waveform
Generator
D
D
D
PORT
DDR
OCn
Q
Q
Q
1
0
2512K–AVR–01/10
OCn
Pin