M55800A Atmel Corporation, M55800A Datasheet - Page 112
M55800A
Manufacturer Part Number
M55800A
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.M55800A.pdf
(29 pages)
4.M55800A.pdf
(256 pages)
5.M55800A.pdf
(28 pages)
Specifications of M55800A
Flash (kbytes)
0 Kbytes
Pin Count
176
Max. Operating Frequency
33 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
58
Ext Interrupts
58
Usb Speed
No
Usb Interface
No
Spi
1
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
72
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3/5.0
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Coprocessor Interface
4.4.4
4-8
Decode stage
Fetch stage
Execute
D[31:0]
Consequences of busy-waiting
MCLK
stage
nCPI
CPA
CPB
ADD
Instr fetch
(ADD)
CPA and CPB are ignored by the ARM7TDMI processor when it does not have a
undefined or coprocessor instruction in the Execute stage of the pipeline.
A summary of coprocessor signaling is listed in Table 4-3 on page 4-7.
A busy-waited coprocessor instruction can be interrupted. If a valid FIQ or IRQ occurs
and the appropriate bit is clear in the CSPR, then the ARM7TDMI processor abandons
the coprocessor instruction, and signals this by taking nCPI HIGH. A coprocessor that
is capable of busy-waiting must monitor nCPI to detect this condition. When the
ARM7TDMI core abandons a coprocessor instruction, the coprocessor also abandons
the instruction, and continues tracking the ARM7TDMI processor pipeline.
ADD
SUB
Instr fetch
(SUB)
Copyright © 1994-2001. All rights reserved.
CDP
SUB
ADD
Instr fetch
(CDP)
CDP
TST
SUB
Instr fetch
(TST)
Instr fetch
(SUB)
Coprocessor
busy waiting
Figure 4-1 Coprocessor busy-wait sequence
CDP
SUB
TST
SUB
TST
Instr fetch
ARM DDI 0029G
SUB
Instr fetch
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