M55800A Atmel Corporation, M55800A Datasheet - Page 96
M55800A
Manufacturer Part Number
M55800A
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.M55800A.pdf
(29 pages)
4.M55800A.pdf
(256 pages)
5.M55800A.pdf
(28 pages)
Specifications of M55800A
Flash (kbytes)
0 Kbytes
Pin Count
176
Max. Operating Frequency
33 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
58
Ext Interrupts
58
Usb Speed
No
Usb Interface
No
Spi
1
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
72
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3/5.0
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Memory Interface
3.6.4
3-26
Byte and halfword accesses
nMREQ
D[15:8]
A[31:0]
BL[3:0]
nWAIT
MCLK
D[7:0]
SEQ
APE
The processor indicates the size of a transfer by use of the MAS[1:0] signal as described
in MAS[1:0] on page 3-11.
Byte, halfword, and word accesses are described in:
•
•
Reads
When a halfword or byte read is performed, a 32-bit memory system can return the
complete 32-bit word, and the processor extracts the valid halfword or byte field from
it. The fields extracted depend on the state of the BIGEND signal, which determines
the endian configuration of the system. See Memory formats on page 2-4.
A word read from 32-bit memory presents the word value on the whole data bus as listed
in Table 3-7.
When connecting 8-bit to 16-bit memory systems to the processor, ensure that the data
is presented to the correct byte lanes on the core as listed in Table 3-7 on page 3-27.
Reads on page 3-26
Writes on page 3-27.
Copyright © 1994-2001. All rights reserved.
0xF
Figure 3-19 Two cycle memory access
0x2
ARM DDI 0029G
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