SAM3N4B Atmel Corporation, SAM3N4B Datasheet - Page 136

• Manufacturer Part Number: SAM3N4B
• Manufacturer: Atmel Corporation

Specifications of SAM3N4B

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 48 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Quadrature Decoder Channels: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 10
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 24
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10.17.4.5
136
Case1
; an instruction sequence follows
Case2
; an instruction sequence follows
Case3
; an instruction sequence follows
BranchTable_Byte
BranchTable_H
CaseA
; an instruction sequence follows
CaseB
; an instruction sequence follows
CaseC
; an instruction sequence follows
ADR.W
TBB
DCB
DCB
DCB
TBH
DCI
DCI
DCI
SAM3N
Examples
[R0, R1]
R0, BranchTable_Byte
0
((Case2-Case1)/2)
((Case3-Case1)/2)
[PC, R1, LSL #1]
((CaseA - BranchTable_H)/2)
((CaseB - BranchTable_H)/2)
((CaseC - BranchTable_H)/2)
; R1 is the index, R0 is the base address of the
; branch table
; Case1 offset calculation
; Case2 offset calculation
; Case3 offset calculation
; R1 is the index, PC is used as base of the
; branch table
; CaseA offset calculation
; CaseB offset calculation
; CaseC offset calculation
11011A–ATARM–04-Oct-10