SAM3N4B Atmel Corporation, SAM3N4B Datasheet - Page 75
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SAM3N4B
Manufacturer Part Number
SAM3N4B
Description
Manufacturer
Atmel Corporation
Specifications of SAM3N4B
Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
48 MHz
Cpu
Cortex-M3
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Quadrature Decoder Channels
2
Usb Speed
No
Usb Interface
No
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
10
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
24
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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10.9
11011A–ATARM–04-Oct-10
Instruction set summary
The processor implements a version of the Thumb instruction set.
ported instructions.
In
For more information on the instructions and operands, see the instruction descriptions.
Table 10-13. Cortex-M3 instructions
Mnemonic
ADC, ADCS
ADD, ADDS
ADD, ADDW
ADR
AND, ANDS
ASR, ASRS
B
BFC
BFI
BIC, BICS
BKPT
BL
BLX
BX
CBNZ
CBZ
CLREX
CLZ
CMN, CMNS
CMP, CMPS
CPSID
CPSIE
DMB
DSB
EOR, EORS
• angle brackets, <>, enclose alternative forms of the operand
• braces, {}, enclose optional operands
• the Operands column is not exhaustive
• Op2 is a flexible second operand that can be either a register or a constant
• most instructions can use an optional condition code suffix.
Table
10-13:
Operands
{Rd,} Rn, Op2
{Rd,} Rn, Op2
{Rd,} Rn, #imm12
Rd, label
{Rd,} Rn, Op2
Rd, Rm, <Rs|#n>
label
Rd, #lsb, #width
Rd, Rn, #lsb, #width
{Rd,} Rn, Op2
#imm
label
Rm
Rm
Rn, label
Rn, label
-
Rd, Rm
Rn, Op2
Rn, Op2
iflags
iflags
-
-
{Rd,} Rn, Op2
Brief description
Add with Carry
Add
Add
Load PC-relative address
Logical AND
Arithmetic Shift Right
Branch
Bit Field Clear
Bit Field Insert
Bit Clear
Breakpoint
Branch with Link
Branch indirect with Link
Branch indirect
Compare and Branch if Non Zero
Compare and Branch if Zero
Clear Exclusive
Count leading zeros
Compare Negative
Compare
Change Processor State, Disable
Interrupts
Change Processor State, Enable
Interrupts
Data Memory Barrier
Data Synchronization Barrier
Exclusive OR
Table 10-13
Flags
N,Z,C,V
N,Z,C
-
-
-
-
-
N,Z,C,V
N,Z,C,V
-
-
-
-
N,Z,C,V
N,Z,C,V
-
N,Z,C
-
-
N,Z,C
-
-
-
-
N,Z,C
SAM3N
lists the sup-
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page 126
page 108
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page 130
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page 102
page 112
page 113
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page 139
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page 108
75
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