SAM3N4B Atmel Corporation, SAM3N4B Datasheet - Page 511

• Manufacturer Part Number: SAM3N4B
• Manufacturer: Atmel Corporation

Specifications of SAM3N4B

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 48 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Quadrature Decoder Channels: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 10
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 24
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 29-10. Transmitter Control
29.5.4
29.5.5
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10
Shift Register
UART_THR
TXEMPTY
TXRDY
UTXD
Peripheral DMA Controller
Test Modes
in UART_THR
Write Data 0
S
Data 0
in UART_THR
Register. The TXRDY bit remains high until a second character is written in UART_THR. As
soon as the first character is completed, the last character written in UART_THR is transferred
into the shift register and TXRDY rises again, showing that the holding register is empty.
When both the Shift Register and UART_THR are empty, i.e., all the characters written in
UART_THR have been processed, the TXEMPTY bit rises after the last stop bit has been
completed.
Both the receiver and the transmitter of the UART are connected to a Peripheral DMA Controller
(PDC) channel.
The peripheral data controller channels are programmed via registers that are mapped within
the UART user interface from the offset 0x100. The status bits are reported in the UART status
register (UART_SR) and can generate an interrupt.
The RXRDY bit triggers the PDC channel data transfer of the receiver. This results in a read of
the data in UART_RHR. The TXRDY bit triggers the PDC channel data transfer of the transmit-
ter. This results in a write of data in UART_THR.
The UART supports three test modes. These modes of operation are programmed by using the
field CHMODE (Channel Mode) in the mode register (UART_MR).
The Automatic Echo mode allows bit-by-bit retransmission. When a bit is received on the URXD
line, it is sent to the UTXD line. The transmitter operates normally, but has no effect on the
UTXD line.
The Local Loopback mode allows the transmitted characters to be received. UTXD and URXD
pins are not used and the output of the transmitter is internally connected to the input of the
receiver. The URXD pin level has no effect and the UTXD line is held high, as in idle state.
The Remote Loopback mode directly connects the URXD pin to the UTXD line. The transmitter
and the receiver are disabled and have no effect. This mode allows a bit-by-bit retransmission.
Write Data 1
Data 0
Data 0
P
stop
S
Data 1
Data 1
P
Data 1
stop
SAM3N
SAM3N
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