SAM3N4C Atmel Corporation, SAM3N4C Datasheet - Page 205

• Manufacturer Part Number: SAM3N4C
• Manufacturer: Atmel Corporation

Specifications of SAM3N4C

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 48 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Quadrature Decoder Channels: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 24
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

11.5.3.1
11.5.4
11.5.5
11011A–ATARM–04-Oct-10
FPB (Flash Patch Breakpoint)
DWT (Data Watchpoint and Trace)
SW-DP and JTAG-DP Selection Mechanism
When the Serial Wire Debug Port is active, TDO/TRACESWO can be used for trace. The asyn-
chronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous trace
can only be used with SW-DP, not JTAG-DP.
Table 11-2.
SW-DP or JTAG-DP mode is selected when JTAGSEL is low. It is not possible to switch directly
between SWJ-DP and JTAG boundary scan operations. A chip reset must be performed after
JTAGSEL is changed.
Debug port selection mechanism is done by sending specific SWDIOTMS sequence. The JTAG-
DP is selected by default after reset.
The FPB:
The FPB unit contains:
The DWT contains four comparators which can be configured to generate the following:
Pin Name
TMS/SWDIO
TCK/SWCLK
TDI
TDO/TRACESWO
• Switch from JTAG-DP to SW-DP. The sequence is:
• Switch from SWD to JTAG. The sequence is:
• Implements hardware breakpoints
• Patches code and data from code space to system space.
• Two literal comparators for matching against literal loads from Code space, and remapping to
• Six instruction comparators for matching against instruction fetches from Code space and
• Alternatively, comparators can also be configured to generate a Breakpoint instruction to the
• PC sampling packets at set intervals
• PC or Data watchpoint packets
a corresponding area in System space.
remapping to a corresponding area in System space.
processor core on a match.
– Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
– Send the 16-bit sequence on SWDIOTMS = 0111100111100111 (0x79E7 MSB first)
– Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
– Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
– Send the 16-bit sequence on SWDIOTMS = 0011110011100111 (0x3CE7 MSB first)
– Send more than 50 SWCLKTCK cycles with SWDIOTMS = 1
SWJ-DP Pin List
JTAG Port
TMS
TDO
TCK
TDI
TRACESWO (optional: trace)
Serial Wire Debug Port
SWCLK
SWDIO
-
SAM3N
205